Searched refs:params_priv (Results 1 – 5 of 5) sorted by relevance
112 struct sdram_params *params_priv) in memory_init() argument116 if (params_priv->ddr_config_t.ddr_type == DDR3 || in memory_init()117 params_priv->ddr_config_t.ddr_type == DDR2) { in memory_init()125 (params_priv->ddr_timing_t.phy_timing.mr[2] & in memory_init()130 (params_priv->ddr_timing_t.phy_timing.mr[3] & in memory_init()135 (params_priv->ddr_timing_t.phy_timing.mr[1] & in memory_init()138 mr0 = params_priv->ddr_timing_t.phy_timing.mr[0]; in memory_init()139 if (params_priv->ddr_config_t.ddr_type == DDR3) { in memory_init()183 (params_priv->ddr_timing_t.phy_timing.mr[1] & in memory_init()187 (params_priv->ddr_timing_t.phy_timing.mr[2] & in memory_init()[all …]
108 struct sdram_params *params_priv) in rkdclk_init() argument140 if (params_priv->ddr_timing_t.freq == 393) { in rkdclk_init()159 if (params_priv->ddr_timing_t.freq == 800) { in rkdclk_init()162 } else if (params_priv->ddr_timing_t.freq == 589) { in rkdclk_init()165 } else if (params_priv->ddr_timing_t.freq == 451) { in rkdclk_init()168 } else if (params_priv->ddr_timing_t.freq == 393) { in rkdclk_init()171 } else if (params_priv->ddr_timing_t.freq == 294) { in rkdclk_init()174 } else if (params_priv->ddr_timing_t.freq == 225) { in rkdclk_init()184 if (params_priv->ddr_timing_t.freq == 800) { in rkdclk_init()452 struct sdram_params *params_priv) in pctl_cfg_grf() argument[all …]
39 struct sdram_params *params_priv) in rkdclk_init() argument48 params_priv->dpll_init_cfg.fbdiv << FBDIV_SHIFT); in rkdclk_init()51 params_priv->dpll_init_cfg.postdiv2 << POSTDIV2_SHIFT | in rkdclk_init()52 params_priv->dpll_init_cfg.postdiv1 << POSTDIV1_SHIFT | in rkdclk_init()53 params_priv->dpll_init_cfg.refdiv << REFDIV_SHIFT); in rkdclk_init()97 struct sdram_params *params_priv) in pctl_cfg_grf() argument104 struct sdram_params *params_priv) in ddr_msch_cfg() argument107 params_priv->ddr_timing_t.noc_timing.d32, in ddr_msch_cfg()109 writel(params_priv->ddr_timing_t.readlatency, in ddr_msch_cfg()111 writel(params_priv->ddr_timing_t.activate.d32, in ddr_msch_cfg()[all …]
61 struct sdram_params *params_priv);63 struct sdram_params *params_priv);64 void ddr_msch_cfg_rbc(struct sdram_params *params_priv,74 struct sdram_params *params_priv);77 struct sdram_params *params_priv);80 struct sdram_params *params_priv);82 struct sdram_params *params_priv);85 struct sdram_params *params_priv);
107 struct sdram_params *params_priv);110 struct sdram_params *params_priv);111 void ddr_msch_cfg_rbc(struct sdram_params *params_priv,121 struct sdram_params *params_priv);125 struct sdram_params *params_priv);129 struct sdram_params *params_priv);131 struct sdram_params *params_priv);134 struct sdram_params *params_priv);