108 		 struct sdram_params *params_priv)  in rkdclk_init()  argument
140 	if (params_priv->ddr_timing_t.freq == 393) {  in rkdclk_init()
159 	if (params_priv->ddr_timing_t.freq == 800) {  in rkdclk_init()
162 	} else if (params_priv->ddr_timing_t.freq == 589) {  in rkdclk_init()
165 	} else if (params_priv->ddr_timing_t.freq == 451) {  in rkdclk_init()
168 	} else if (params_priv->ddr_timing_t.freq == 393) {  in rkdclk_init()
171 	} else if (params_priv->ddr_timing_t.freq == 294) {  in rkdclk_init()
174 	} else if (params_priv->ddr_timing_t.freq == 225) {  in rkdclk_init()
184 	if (params_priv->ddr_timing_t.freq == 800) {  in rkdclk_init()
452 		  struct sdram_params *params_priv)  in pctl_cfg_grf()  argument
454 	if (params_priv->ddr_config_t.ddr_type == DDR3 ||  in pctl_cfg_grf()
455 	    params_priv->ddr_config_t.ddr_type == DDR2)  in pctl_cfg_grf()
464 		  struct sdram_params *params_priv)  in ddr_msch_cfg()  argument
466 	writel(BWRATIO_HALF_BW | params_priv->ddr_timing_t.noc_timing.d32,  in ddr_msch_cfg()
468 	writel(params_priv->ddr_timing_t.readlatency,  in ddr_msch_cfg()
472 void ddr_msch_cfg_rbc(struct sdram_params *params_priv,  in ddr_msch_cfg_rbc()  argument
477 	if (params_priv->ddr_config_t.bank == 3) {  in ddr_msch_cfg_rbc()
479 		if (params_priv->ddr_config_t.col == 10)  in ddr_msch_cfg_rbc()
481 		else if (params_priv->ddr_config_t.col == 11)  in ddr_msch_cfg_rbc()
486 	} else if (params_priv->ddr_config_t.bank == 2) {  in ddr_msch_cfg_rbc()
514 		struct sdram_params *params_priv)  in set_ds_odt()  argument
527 	if (params_priv->ddr_config_t.ddr_type == LPDDR2) {  in set_ds_odt()
533 		if (params_priv->ddr_timing_t.freq >  in set_ds_odt()
581 			struct sdram_params *params_priv)  in enable_ddr_standby()  argument
590 	if (params_priv->stdby_idle == 128) {  in enable_ddr_standby()
591 		if (params_priv->ddr_timing_t.freq == 451)  in enable_ddr_standby()
592 			params_priv->stdby_idle = 105;  in enable_ddr_standby()
593 		else if (params_priv->ddr_timing_t.freq == 393)  in enable_ddr_standby()
594 			params_priv->stdby_idle = 10;  in enable_ddr_standby()
596 	writel(params_priv->stdby_idle << IDLE_TH_SHIFT |  in enable_ddr_standby()
686 				struct sdram_params *params_priv)  in modify_sdram_params()  argument
690 	u32 nMHz = params_priv->ddr_timing_t.freq;  in modify_sdram_params()
693 		       params_priv->ddr_config_t.col +  in modify_sdram_params()
694 		       params_priv->ddr_config_t.cs0_row +  in modify_sdram_params()
695 		       params_priv->ddr_config_t.bank);  in modify_sdram_params()
698 	switch (params_priv->ddr_config_t.ddr_type) {  in modify_sdram_params()
782 			  struct sdram_params *params_priv)  in modify_data_training()  argument
826 		      struct sdram_params *params_priv)  in enable_low_power()  argument
830 	if (params_priv->idle_pd == 48 && params_priv->idle_sr == 10) {  in enable_low_power()
831 		if (params_priv->ddr_timing_t.freq == 451) {  in enable_low_power()
832 			params_priv->idle_sr = 28;  in enable_low_power()
833 			params_priv->idle_pd = 7;  in enable_low_power()
834 		} else if (params_priv->ddr_timing_t.freq == 393) {  in enable_low_power()
835 			params_priv->idle_sr = 31;  in enable_low_power()
836 			params_priv->idle_pd = 15;  in enable_low_power()
840 			params_priv->idle_pd << PD_IDLE_SHIFT);  in enable_low_power()
843 			params_priv->idle_sr | HW_EXIT_IDLE_EN);  in enable_low_power()