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Searched refs:mbar_writeLong (Results 1 – 7 of 7) sorted by relevance

/OK3568_Linux_fs/u-boot/board/freescale/m5249evb/
H A Dm5249evb.c69 mbar_writeLong(MCFSIM_DACR0, 0x00003324); in dram_init()
72 mbar_writeLong(MCFSIM_DMR0, 0x01fc0001); in dram_init()
75 mbar_writeLong(MCFSIM_DACR0, 0x0000332c); /* Set DACR0[IP] (bit 3) */ in dram_init()
80 mbar_writeLong(MCFSIM_DACR0, 0x0000b324); /* Enable the refresh bit, DACR0[RE] (bit 15) */ in dram_init()
84 mbar_writeLong(MCFSIM_DACR0, 0x0000b364); /* Enable DACR0[IMRS] (bit 6); RE remains enabled */ in dram_init()
/OK3568_Linux_fs/u-boot/board/freescale/m5253evbe/
H A Dm5253evbe.c40 mbar_writeLong(MCFSIM_DACR0, 0x00002320); in dram_init()
45 mbar_writeLong(MCFSIM_DMR0, dramsize | 1); in dram_init()
48 mbar_writeLong(MCFSIM_DACR0, 0x00002328); in dram_init()
56 mbar_writeLong(MCFSIM_DACR0, in dram_init()
64 mbar_writeLong(MCFSIM_DACR0, in dram_init()
/OK3568_Linux_fs/u-boot/board/freescale/m5253demo/
H A Dm5253demo.c43 mbar_writeLong(MCFSIM_DACR0, 0x00003224); in dram_init()
49 mbar_writeLong(MCFSIM_DMR0, temp | 1); in dram_init()
52 mbar_writeLong(MCFSIM_DACR0, 0x0000322c); in dram_init()
62 mbar_writeLong(MCFSIM_DACR0, in dram_init()
70 mbar_writeLong(MCFSIM_DACR0, in dram_init()
/OK3568_Linux_fs/u-boot/arch/m68k/cpu/mcf52x2/
H A Dcpu_init.c266 mbar_writeLong(MCF_FMPLL_SYNCR, CONFIG_SYS_MCF_SYNCR); in cpu_init_f()
269 mbar_writeLong(MCF_FMPLL_SYNCR, in cpu_init_f()
695 mbar_writeLong(MCFSIM_IMR, 0xfffffbff); in cpu_init_f()
H A Dinterrupts.c89 mbar_writeLong(MCFSIM_IMR, mbar_readLong(MCFSIM_IMR) & ~0x00000400); in dtimer_intr_setup()
/OK3568_Linux_fs/u-boot/arch/m68k/include/asm/
H A Dm5249.h19 #define mbar_writeLong(x,y) *((volatile unsigned long *) (CONFIG_SYS_MBAR + x)) = y macro
H A Dm5271.h18 #define mbar_writeLong(x,y) *((volatile unsigned long *) (CONFIG_SYS_MBAR + x)) = y macro