1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * (C) Copyright 2000-2004
3*4882a593Smuzhiyun * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
6*4882a593Smuzhiyun * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
7*4882a593Smuzhiyun *
8*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
9*4882a593Smuzhiyun */
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun #include <common.h>
12*4882a593Smuzhiyun #include <watchdog.h>
13*4882a593Smuzhiyun #include <asm/processor.h>
14*4882a593Smuzhiyun #include <asm/immap.h>
15*4882a593Smuzhiyun #include <asm/io.h>
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun #ifdef CONFIG_M5272
interrupt_init(void)18*4882a593Smuzhiyun int interrupt_init(void)
19*4882a593Smuzhiyun {
20*4882a593Smuzhiyun intctrl_t *intp = (intctrl_t *) (MMAP_INTC);
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun /* disable all external interrupts */
23*4882a593Smuzhiyun out_be32(&intp->int_icr1, 0x88888888);
24*4882a593Smuzhiyun out_be32(&intp->int_icr2, 0x88888888);
25*4882a593Smuzhiyun out_be32(&intp->int_icr3, 0x88888888);
26*4882a593Smuzhiyun out_be32(&intp->int_icr4, 0x88888888);
27*4882a593Smuzhiyun out_be32(&intp->int_pitr, 0x00000000);
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun /* initialize vector register */
30*4882a593Smuzhiyun out_8(&intp->int_pivr, 0x40);
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun enable_interrupts();
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun return 0;
35*4882a593Smuzhiyun }
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun #if defined(CONFIG_MCFTMR)
dtimer_intr_setup(void)38*4882a593Smuzhiyun void dtimer_intr_setup(void)
39*4882a593Smuzhiyun {
40*4882a593Smuzhiyun intctrl_t *intp = (intctrl_t *) (CONFIG_SYS_INTR_BASE);
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun clrbits_be32(&intp->int_icr1, INT_ICR1_TMR3MASK);
43*4882a593Smuzhiyun setbits_be32(&intp->int_icr1, CONFIG_SYS_TMRINTR_PRI);
44*4882a593Smuzhiyun }
45*4882a593Smuzhiyun #endif /* CONFIG_MCFTMR */
46*4882a593Smuzhiyun #endif /* CONFIG_M5272 */
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun #if defined(CONFIG_M5208) || defined(CONFIG_M5282) || \
49*4882a593Smuzhiyun defined(CONFIG_M5271) || defined(CONFIG_M5275)
interrupt_init(void)50*4882a593Smuzhiyun int interrupt_init(void)
51*4882a593Smuzhiyun {
52*4882a593Smuzhiyun int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun /* Make sure all interrupts are disabled */
55*4882a593Smuzhiyun #if defined(CONFIG_M5208)
56*4882a593Smuzhiyun out_be32(&intp->imrl0, 0xffffffff);
57*4882a593Smuzhiyun out_be32(&intp->imrh0, 0xffffffff);
58*4882a593Smuzhiyun #else
59*4882a593Smuzhiyun setbits_be32(&intp->imrl0, 0x1);
60*4882a593Smuzhiyun #endif
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun enable_interrupts();
63*4882a593Smuzhiyun return 0;
64*4882a593Smuzhiyun }
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun #if defined(CONFIG_MCFTMR)
dtimer_intr_setup(void)67*4882a593Smuzhiyun void dtimer_intr_setup(void)
68*4882a593Smuzhiyun {
69*4882a593Smuzhiyun int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun out_8(&intp->icr0[CONFIG_SYS_TMRINTR_NO], CONFIG_SYS_TMRINTR_PRI);
72*4882a593Smuzhiyun clrbits_be32(&intp->imrl0, 0x00000001);
73*4882a593Smuzhiyun clrbits_be32(&intp->imrl0, CONFIG_SYS_TMRINTR_MASK);
74*4882a593Smuzhiyun }
75*4882a593Smuzhiyun #endif /* CONFIG_MCFTMR */
76*4882a593Smuzhiyun #endif /* CONFIG_M5282 | CONFIG_M5271 | CONFIG_M5275 */
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun #if defined(CONFIG_M5249) || defined(CONFIG_M5253)
interrupt_init(void)79*4882a593Smuzhiyun int interrupt_init(void)
80*4882a593Smuzhiyun {
81*4882a593Smuzhiyun enable_interrupts();
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun return 0;
84*4882a593Smuzhiyun }
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun #if defined(CONFIG_MCFTMR)
dtimer_intr_setup(void)87*4882a593Smuzhiyun void dtimer_intr_setup(void)
88*4882a593Smuzhiyun {
89*4882a593Smuzhiyun mbar_writeLong(MCFSIM_IMR, mbar_readLong(MCFSIM_IMR) & ~0x00000400);
90*4882a593Smuzhiyun mbar_writeByte(MCFSIM_TIMER2ICR, CONFIG_SYS_TMRINTR_PRI);
91*4882a593Smuzhiyun }
92*4882a593Smuzhiyun #endif /* CONFIG_MCFTMR */
93*4882a593Smuzhiyun #endif /* CONFIG_M5249 || CONFIG_M5253 */
94