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Searched refs:cs_ena (Results 1 – 13 of 13) sorted by relevance

/OK3568_Linux_fs/u-boot/drivers/ddr/marvell/axp/
H A Dddr3_spd.c582 u32 cs, cl, cs_num, cs_ena; local
654 cs_ena = 0;
656 cs_ena = ddr3_get_cs_ena_from_reg();
664 !(cs_ena & (1 << cs))) {
666 cs_ena |= (0x1 << cs);
668 cs_ena |= (0x3 << cs);
670 cs_ena |= (0x7 << cs);
672 cs_ena |= (0xF << cs);
682 if (cs_ena > 0xF) {
898 if (cs_ena & (1 << cs) & DIMM_CS_BITMAP) {
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H A Dddr3_write_leveling.c87 reg |= (dram_info->cs_ena << (REG_DRAM_TRAINING_CS_OFFS)); in ddr3_write_leveling_hw()
108 if (dram_info->cs_ena & (1 << cs)) { in ddr3_write_leveling_hw()
230 if (dram_info->cs_ena & (1 << cs)) { in ddr3_wl_supplement()
432 if (dram_info->cs_ena & (1 << cs)) { in ddr3_wl_supplement()
510 reg |= (dram_info->cs_ena << (REG_DRAM_TRAINING_CS_OFFS)); in ddr3_write_leveling_hw_reg_dimm()
531 if (dram_info->cs_ena & (1 << cs)) { in ddr3_write_leveling_hw_reg_dimm()
620 if (dram_info->cs_ena & (1 << cs)) { in ddr3_write_leveling_hw_reg_dimm()
680 if (dram_info->cs_ena & (1 << cs)) { in ddr3_write_leveling_sw()
683 reg |= odt_static[dram_info->cs_ena][cs]; in ddr3_write_leveling_sw()
723 if (dram_info->cs_ena & (1 << cs)) { in ddr3_write_leveling_sw()
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H A Dddr3_hw_training.c95 dram_info.cs_ena = ddr3_get_cs_ena_from_reg(); in ddr3_hw_training()
229 if (dram_info.cs_ena > 1) { in ddr3_hw_training()
320 if (dram_info.cs_ena > 1) { in ddr3_hw_training()
456 dram_info.cs_ena = 1; in ddr3_hw_training()
666 reg = (dram_info->cs_ena << REG_DRAM_TRAINING_CS_OFFS) | in ddr3_load_patterns()
714 tmp_cs = dram_info->cs_ena; in ddr3_save_training()
892 dram_info->cs_ena = 0x1; in ddr3_check_if_resume_mode()
901 dram_info->cs_ena = ddr3_get_cs_ena_from_reg(); in ddr3_check_if_resume_mode()
957 dram_info->cs_ena = 1; in ddr3_training_suspend_resume()
1090 u32 cs_ena, reg; in ddr3_odt_read_dynamic_config() local
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H A Dddr3_init.c143 u32 cs_ena = ddr3_get_cs_ena_from_reg(); in ddr3_restore_and_set_final_windows() local
170 if (cs_ena & (1 << cs)) { in ddr3_restore_and_set_final_windows()
186 if (cs_ena & (1 << cs)) { in ddr3_restore_and_set_final_windows()
199 u32 cs_ena = ddr3_get_cs_ena_from_reg(); in ddr3_save_and_set_training_windows() local
233 if (cs_ena & (1 << cs)) { in ddr3_save_and_set_training_windows()
1073 u32 cs_ena = ddr3_get_cs_ena_from_reg(); in ddr3_get_cs_num_from_reg() local
1078 if (cs_ena & (1 << cs)) in ddr3_get_cs_num_from_reg()
H A Dddr3_dfs.c197 if (dram_info->cs_ena & (1 << cs)) { in ddr3_dfs_high_2_low()
443 if (dram_info->cs_ena & (1 << cs)) in ddr3_dfs_high_2_low()
469 if (dram_info->cs_ena & (1 << cs)) { in ddr3_dfs_high_2_low()
677 if (dram_info->cs_ena & (1 << cs)) { in ddr3_dfs_high_2_low()
1006 if (dram_info->cs_ena & (1 << cs)) { in ddr3_dfs_low_2_high()
1010 reg |= odt_static[dram_info->cs_ena][cs]; in ddr3_dfs_low_2_high()
1138 if (dram_info->cs_ena & (1 << cs)) in ddr3_dfs_low_2_high()
1164 if (dram_info->cs_ena & (1 << cs)) { in ddr3_dfs_low_2_high()
1437 if (dram_info->cs_ena & (1 << cs)) { in ddr3_dfs_low_2_high()
H A Dddr3_dqs.c152 if (dram_info->cs_ena & (1 << cs)) { in ddr3_dqs_centralization_rx()
234 if (dram_info->cs_ena & (1 << cs)) { in ddr3_dqs_centralization_tx()
335 if (dram_info->cs_ena & (1 << cs_tmp)) in ddr3_find_adll_limits()
1336 if (dram_info->cs_ena & (1 << cs)) { in ddr3_load_dqs_patterns()
1339 if (dram_info->cs_ena & (1 << cs_tmp)) in ddr3_load_dqs_patterns()
H A Dddr3_read_leveling.c75 reg |= (dram_info->cs_ena << REG_DRAM_TRAINING_CS_OFFS); in ddr3_read_leveling_hw()
99 if (dram_info->cs_ena & (1 << cs)) { in ddr3_read_leveling_hw()
197 reg = (dram_info->cs_ena << REG_DRAM_TRAINING_CS_OFFS) | in ddr3_read_leveling_sw()
H A Dxor.c52 if (dram_info->cs_ena & (1 << ui)) { in mv_sys_xor_init()
H A Dddr3_hw_training.h254 u32 cs_ena; member
H A Dddr3_pbs.c1561 if (dram_info->cs_ena & (1 << cs)) { in ddr3_load_pbs_patterns()
1564 if (dram_info->cs_ena & (1 << cs_tmp)) in ddr3_load_pbs_patterns()
/OK3568_Linux_fs/u-boot/drivers/ddr/marvell/a38x/
H A Dddr3_init.c181 u32 cs_ena = sys_env_get_cs_ena_from_reg(); in ddr3_restore_and_set_final_windows() local
195 if (ddr3_fast_path_dynamic_cs_size_config(cs_ena) != MV_OK) in ddr3_restore_and_set_final_windows()
201 if (cs_ena & (1 << cs)) { in ddr3_restore_and_set_final_windows()
213 u32 cs_ena; in ddr3_save_and_set_training_windows() local
232 cs_ena = tm->interface_params[0].as_bus_params[0].cs_bitmask; in ddr3_save_and_set_training_windows()
246 if (cs_ena & (1 << cs)) { in ddr3_save_and_set_training_windows()
519 u32 cs_ena = sys_env_get_cs_ena_from_reg(); in ddr3_get_cs_num_from_reg() local
524 if (cs_ena & (1 << cs)) in ddr3_get_cs_num_from_reg()
579 int ddr3_fast_path_dynamic_cs_size_config(u32 cs_ena) in ddr3_fast_path_dynamic_cs_size_config() argument
594 if (cs_ena & (1 << cs)) { in ddr3_fast_path_dynamic_cs_size_config()
H A Dxor.c28 void mv_sys_xor_init(u32 num_of_cs, u32 cs_ena, u32 cs_size, u32 base_delta) in mv_sys_xor_init() argument
52 if (cs_ena & (1 << ui)) { in mv_sys_xor_init()
331 u32 cs_ena = 0; in ddr3_new_tip_ecc_scrub() local
337 cs_ena |= 1 << cs_c; in ddr3_new_tip_ecc_scrub()
339 mv_sys_xor_init(max_cs, cs_ena, 0x80000000, 0); in ddr3_new_tip_ecc_scrub()
H A Dddr3_init.h350 int ddr3_fast_path_dynamic_cs_size_config(u32 cs_ena);
351 void ddr3_fast_path_static_cs_size_config(u32 cs_ena);