Searched refs:con_offset (Results 1 – 8 of 8) sorted by relevance
| /OK3568_Linux_fs/u-boot/drivers/clk/rockchip/ |
| H A D | clk_pll.c | 277 rk_setreg(base + pll->con_offset + 0x4, in rk3036_pll_set_rate()
280 rk_clrsetreg(base + pll->con_offset, in rk3036_pll_set_rate()
285 rk_clrsetreg(base + pll->con_offset + 0x4, in rk3036_pll_set_rate()
291 rk_clrsetreg(base + pll->con_offset + 0x4, in rk3036_pll_set_rate()
294 writel((readl(base + pll->con_offset + 0x8) & in rk3036_pll_set_rate()
297 base + pll->con_offset + 0x8); in rk3036_pll_set_rate()
301 rk_clrreg(base + pll->con_offset + 0x4, in rk3036_pll_set_rate()
305 while ((timeout > 0) && !(readl(base + pll->con_offset + 0x4) & (1 << pll->lock_shift))) { in rk3036_pll_set_rate()
310 if (!(readl(base + pll->con_offset + 0x4) & (1 << pll->lock_shift))) in rk3036_pll_set_rate()
319 pll, readl(base + pll->con_offset), in rk3036_pll_set_rate()
[all …]
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| /OK3568_Linux_fs/u-boot/arch/arm/include/asm/arch-rockchip/ |
| H A D | clock.h | 59 .con_offset = _con, \
119 unsigned int con_offset; member
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| /OK3568_Linux_fs/kernel/arch/arm/mach-s3c/ |
| H A D | gpio-samsung.c | 589 unsigned con_offset = offset; in samsung_gpiolib_4bit2_output() local
591 if (con_offset > 7) in samsung_gpiolib_4bit2_output()
592 con_offset -= 8; in samsung_gpiolib_4bit2_output()
597 con &= ~(0xf << con_4bit_shift(con_offset)); in samsung_gpiolib_4bit2_output()
598 con |= 0x1 << con_4bit_shift(con_offset); in samsung_gpiolib_4bit2_output()
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| /OK3568_Linux_fs/kernel/drivers/clk/samsung/ |
| H A D | clk.h | 252 int con_offset; member
265 .con_offset = _con, \
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| H A D | clk-pll.c | 1387 pll->con_reg = base + pll_clk->con_offset; in _samsung_clk_register_pll()
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| /OK3568_Linux_fs/kernel/drivers/clk/rockchip/ |
| H A D | clk.h | 566 int con_offset; member
592 .con_offset = _con, \
603 u8 num_parents, int con_offset, int grf_lock_offset,
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| H A D | clk.c | 456 list->con_offset, grf_lock_offset, in rockchip_clk_register_plls()
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| H A D | clk-pll.c | 1627 u8 num_parents, int con_offset, int grf_lock_offset, in rockchip_clk_register_pll() argument
1758 pll->reg_base = ctx->reg_base + con_offset; in rockchip_clk_register_pll()
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