Searched refs:clock_manager_base (Results 1 – 4 of 4) sorted by relevance
| /OK3568_Linux_fs/u-boot/arch/arm/mach-socfpga/ |
| H A D | clock_manager_gen5.c | 14 static const struct socfpga_clock_manager *clock_manager_base = variable
23 writel(val, &clock_manager_base->bypass); in cm_write_bypass()
30 writel(val, &clock_manager_base->ctrl); in cm_write_ctrl()
84 readl(&clock_manager_base->per_pll.en), in cm_basic_init()
85 &clock_manager_base->per_pll.en); in cm_basic_init()
94 &clock_manager_base->main_pll.en); in cm_basic_init()
96 writel(0, &clock_manager_base->sdr_pll.en); in cm_basic_init()
99 writel(0, &clock_manager_base->per_pll.en); in cm_basic_init()
108 &clock_manager_base->main_pll.vco); in cm_basic_init()
111 &clock_manager_base->per_pll.vco); in cm_basic_init()
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| H A D | clock_manager_arria10.c | 80 static const struct socfpga_clock_manager *clock_manager_base = variable
481 &clock_manager_base->main_pll.vco1); in cm_pll_ramp_main()
486 main_cfg->vco1_numer, &clock_manager_base->main_pll.vco1); in cm_pll_ramp_main()
511 &clock_manager_base->per_pll.vco1); in cm_pll_ramp_periph()
516 per_cfg->vco1_numer, &clock_manager_base->per_pll.vco1); in cm_pll_ramp_periph()
568 &clock_manager_base->main_pll.enr); in cm_full_cfg()
571 writel(0, &clock_manager_base->per_pll.en); in cm_full_cfg()
575 &clock_manager_base->main_pll.bypasss); in cm_full_cfg()
577 &clock_manager_base->per_pll.bypasss); in cm_full_cfg()
587 &clock_manager_base->main_pll.vco0); in cm_full_cfg()
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| H A D | clock_manager.c | 14 static const struct socfpga_clock_manager *clock_manager_base = variable
23 inter_val = readl(&clock_manager_base->inter) & mask; in cm_wait_for_lock()
25 inter_val = readl(&clock_manager_base->stat) & mask; in cm_wait_for_lock()
40 return wait_for_bit_le32(&clock_manager_base->stat, in cm_wait_for_fsm()
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| /OK3568_Linux_fs/u-boot/drivers/mmc/ |
| H A D | socfpga_dw_mmc.c | 20 static const struct socfpga_clock_manager *clock_manager_base = variable
44 clrbits_le32(&clock_manager_base->per_pll.en, in socfpga_dwmci_clksel()
55 setbits_le32(&clock_manager_base->per_pll.en, in socfpga_dwmci_clksel()
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