1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright (C) 2013-2017 Altera Corporation <www.altera.com>
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #include <common.h>
8*4882a593Smuzhiyun #include <wait_bit.h>
9*4882a593Smuzhiyun #include <asm/io.h>
10*4882a593Smuzhiyun #include <asm/arch/clock_manager.h>
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun DECLARE_GLOBAL_DATA_PTR;
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun static const struct socfpga_clock_manager *clock_manager_base =
15*4882a593Smuzhiyun (struct socfpga_clock_manager *)SOCFPGA_CLKMGR_ADDRESS;
16*4882a593Smuzhiyun
cm_wait_for_lock(u32 mask)17*4882a593Smuzhiyun void cm_wait_for_lock(u32 mask)
18*4882a593Smuzhiyun {
19*4882a593Smuzhiyun u32 inter_val;
20*4882a593Smuzhiyun u32 retry = 0;
21*4882a593Smuzhiyun do {
22*4882a593Smuzhiyun #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
23*4882a593Smuzhiyun inter_val = readl(&clock_manager_base->inter) & mask;
24*4882a593Smuzhiyun #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
25*4882a593Smuzhiyun inter_val = readl(&clock_manager_base->stat) & mask;
26*4882a593Smuzhiyun #endif
27*4882a593Smuzhiyun /* Wait for stable lock */
28*4882a593Smuzhiyun if (inter_val == mask)
29*4882a593Smuzhiyun retry++;
30*4882a593Smuzhiyun else
31*4882a593Smuzhiyun retry = 0;
32*4882a593Smuzhiyun if (retry >= 10)
33*4882a593Smuzhiyun break;
34*4882a593Smuzhiyun } while (1);
35*4882a593Smuzhiyun }
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun /* function to poll in the fsm busy bit */
cm_wait_for_fsm(void)38*4882a593Smuzhiyun int cm_wait_for_fsm(void)
39*4882a593Smuzhiyun {
40*4882a593Smuzhiyun return wait_for_bit_le32(&clock_manager_base->stat,
41*4882a593Smuzhiyun CLKMGR_STAT_BUSY, false, 20000, false);
42*4882a593Smuzhiyun }
43*4882a593Smuzhiyun
set_cpu_clk_info(void)44*4882a593Smuzhiyun int set_cpu_clk_info(void)
45*4882a593Smuzhiyun {
46*4882a593Smuzhiyun /* Calculate the clock frequencies required for drivers */
47*4882a593Smuzhiyun cm_get_l4_sp_clk_hz();
48*4882a593Smuzhiyun cm_get_mmc_controller_clk_hz();
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun gd->bd->bi_arm_freq = cm_get_mpu_clk_hz() / 1000000;
51*4882a593Smuzhiyun gd->bd->bi_dsp_freq = 0;
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
54*4882a593Smuzhiyun gd->bd->bi_ddr_freq = cm_get_sdram_clk_hz() / 1000000;
55*4882a593Smuzhiyun #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
56*4882a593Smuzhiyun gd->bd->bi_ddr_freq = 0;
57*4882a593Smuzhiyun #endif
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun return 0;
60*4882a593Smuzhiyun }
61*4882a593Smuzhiyun
do_showclocks(cmd_tbl_t * cmdtp,int flag,int argc,char * const argv[])62*4882a593Smuzhiyun int do_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
63*4882a593Smuzhiyun {
64*4882a593Smuzhiyun cm_print_clock_quick_summary();
65*4882a593Smuzhiyun return 0;
66*4882a593Smuzhiyun }
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun U_BOOT_CMD(
69*4882a593Smuzhiyun clocks, CONFIG_SYS_MAXARGS, 1, do_showclocks,
70*4882a593Smuzhiyun "display clocks",
71*4882a593Smuzhiyun ""
72*4882a593Smuzhiyun );
73