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Searched refs:bus_act_mask (Results 1 – 12 of 12) sorted by relevance

/OK3568_Linux_fs/u-boot/drivers/ddr/marvell/a38x/
H A Dddr3_hws_hw_training.c28 if (DDR3_IS_ECC_PUP4_MODE(tm->bus_act_mask) || in ddr3_if_ecc_enabled()
29 DDR3_IS_ECC_PUP3_MODE(tm->bus_act_mask)) in ddr3_if_ecc_enabled()
40 if (DDR3_IS_ECC_PUP3_MODE(tm->bus_act_mask)) { in ddr3_pre_algo_config()
48 if ((DDR3_IS_ECC_PUP4_MODE(tm->bus_act_mask)) || in ddr3_pre_algo_config()
49 (DDR3_IS_ECC_PUP3_MODE(tm->bus_act_mask))) { in ddr3_pre_algo_config()
79 if ((DDR3_IS_ECC_PUP4_MODE(tm->bus_act_mask)) || in ddr3_post_algo_config()
80 (DDR3_IS_ECC_PUP3_MODE(tm->bus_act_mask))) { in ddr3_post_algo_config()
H A Dddr3_training_pbs.c92 VALIDATE_ACTIVE(tm->bus_act_mask, pup); in ddr3_tip_pbs()
105 VALIDATE_ACTIVE(tm->bus_act_mask, pup); in ddr3_tip_pbs()
181 VALIDATE_ACTIVE(tm->bus_act_mask, pup); in ddr3_tip_pbs()
340 VALIDATE_ACTIVE(tm->bus_act_mask, pup); in ddr3_tip_pbs()
355 VALIDATE_ACTIVE(tm->bus_act_mask, pup); in ddr3_tip_pbs()
378 VALIDATE_ACTIVE(tm->bus_act_mask, pup); in ddr3_tip_pbs()
405 VALIDATE_ACTIVE(tm->bus_act_mask, pup); in ddr3_tip_pbs()
466 VALIDATE_ACTIVE(tm->bus_act_mask, pup); in ddr3_tip_pbs()
483 VALIDATE_ACTIVE(tm->bus_act_mask, pup); in ddr3_tip_pbs()
632 VALIDATE_ACTIVE(tm->bus_act_mask, pup); in ddr3_tip_pbs()
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H A Dddr3_training_leveling.c331 VALIDATE_ACTIVE(tm->bus_act_mask, bus_num); in ddr3_tip_dynamic_read_leveling()
397 VALIDATE_ACTIVE(tm->bus_act_mask, bus_num); in ddr3_tip_dynamic_read_leveling()
545 VALIDATE_ACTIVE(tm->bus_act_mask, bus_num); in ddr3_tip_dynamic_per_bit_read_leveling()
729 VALIDATE_ACTIVE(tm->bus_act_mask, bus_num); in ddr3_tip_dynamic_per_bit_read_leveling()
803 VALIDATE_ACTIVE(tm->bus_act_mask, in ddr3_tip_dynamic_per_bit_read_leveling()
835 VALIDATE_ACTIVE(tm->bus_act_mask, bus_num); in ddr3_tip_dynamic_per_bit_read_leveling()
936 VALIDATE_ACTIVE(tm->bus_act_mask, bus_cnt); in ddr3_tip_calc_cs_mask()
1117 VALIDATE_ACTIVE(tm->bus_act_mask, in ddr3_tip_dynamic_write_leveling()
1195 VALIDATE_ACTIVE(tm->bus_act_mask, bus_cnt); in ddr3_tip_dynamic_write_leveling()
1318 VALIDATE_ACTIVE(tm->bus_act_mask, bus_id); in ddr3_tip_dynamic_write_leveling_supp()
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H A Dddr3_training_static.c117 VALIDATE_ACTIVE(tm->bus_act_mask, bus_index); in ddr3_tip_static_round_trip_arr_build()
171 VALIDATE_ACTIVE(tm->bus_act_mask, bus_index); in ddr3_tip_write_leveling_static_config()
255 VALIDATE_ACTIVE(tm->bus_act_mask, bus_index); in ddr3_tip_read_leveling_static_config()
319 VALIDATE_ACTIVE(tm->bus_act_mask, bus_index); in ddr3_tip_read_leveling_static_config()
516 VALIDATE_ACTIVE(tm->bus_act_mask, phy_id); in ddr3_tip_configure_phy()
H A Dddr3_debug.c126 VALIDATE_ACTIVE(tm->bus_act_mask, bus_id); in ddr3_tip_reg_dump()
137 VALIDATE_ACTIVE(tm->bus_act_mask, bus_id); in ddr3_tip_reg_dump()
501 VALIDATE_ACTIVE(tm->bus_act_mask, bus_id); in ddr3_tip_print_stability_log()
542 VALIDATE_ACTIVE(tm->bus_act_mask, bus_id); in ddr3_tip_print_stability_log()
672 VALIDATE_ACTIVE(tm->bus_act_mask, bus_id); in read_adll_value()
705 VALIDATE_ACTIVE(tm->bus_act_mask, bus_id); in write_adll_value()
771 VALIDATE_ACTIVE(tm->bus_act_mask, bus_cnt); in ddr3_tip_print_adll()
1170 VALIDATE_ACTIVE(tm->bus_act_mask, j); in print_adll()
1378 VALIDATE_ACTIVE(tm->bus_act_mask, pup); in ddr3_tip_run_sweep_test()
1428 printf("\tbus_act_mask: 0x%x\n", topology_db->bus_act_mask); in print_topology()
H A Dddr3_training_ip_engine.c348 if (IS_ACTIVE(tm->bus_act_mask, pup_id) == 1) in ddr3_tip_ip_training()
647 VALIDATE_ACTIVE(tm->bus_act_mask, pup_cnt); in ddr3_tip_read_training_result()
1042 VALIDATE_ACTIVE(tm->bus_act_mask, pup_id); in ddr3_tip_ip_training_wrapper()
1112 VALIDATE_ACTIVE(tm->bus_act_mask, pup_id); in ddr3_tip_ip_training_wrapper()
1147 VALIDATE_ACTIVE(tm->bus_act_mask, pup_id); in ddr3_tip_ip_training_wrapper()
1185 VALIDATE_ACTIVE(tm->bus_act_mask, bus_cnt); in ddr3_tip_load_phy_values()
1287 VALIDATE_ACTIVE(tm->bus_act_mask, in ddr3_tip_training_ip_test()
1330 if (DDR3_IS_16BIT_DRAM_MODE(tm->bus_act_mask) == 0) in ddr3_tip_get_pattern_table()
1340 if (DDR3_IS_ECC_PUP3_MODE(tm->bus_act_mask)) in ddr3_tip_get_mask_results_dq_reg()
1350 if (DDR3_IS_ECC_PUP3_MODE(tm->bus_act_mask)) in ddr3_tip_get_mask_results_pup_reg_map()
H A Dddr3_training_centralization.c111 VALIDATE_ACTIVE(tm->bus_act_mask, bus_id); in ddr3_tip_centralization()
141 VALIDATE_ACTIVE(tm->bus_act_mask, bus_id); in ddr3_tip_centralization()
357 VALIDATE_ACTIVE(tm->bus_act_mask, bus_id); in ddr3_tip_centralization()
551 VALIDATE_ACTIVE(tm->bus_act_mask, pup_id); in ddr3_tip_special_rx()
706 VALIDATE_ACTIVE(tm->bus_act_mask, bus_id); in ddr3_tip_print_centralization_result()
H A Dddr3_training_hw_algo.c244 (tm->bus_act_mask, pup); in ddr3_tip_vref()
268 VALIDATE_ACTIVE(tm->bus_act_mask, pup); in ddr3_tip_vref()
282 VALIDATE_ACTIVE(tm->bus_act_mask, pup); in ddr3_tip_vref()
610 VALIDATE_ACTIVE(tm->bus_act_mask, pup); in ddr3_tip_vref()
H A Dddr3_training.c273 VALIDATE_ACTIVE(tm->bus_act_mask, bus_cnt); in calc_cs_num()
337 VALIDATE_ACTIVE(tm->bus_act_mask, bus_index); in hws_ddr3_tip_init_controller()
373 (DDR3_IS_16BIT_DRAM_MODE(tm->bus_act_mask) in hws_ddr3_tip_init_controller()
471 VALIDATE_ACTIVE(tm->bus_act_mask, bus_cnt); in hws_ddr3_tip_init_controller()
729 VALIDATE_ACTIVE(tm->bus_act_mask, bus_cnt); in ddr3_tip_rank_control()
764 VALIDATE_ACTIVE(tm->bus_act_mask, bus_cnt); in ddr3_tip_pad_inv()
995 VALIDATE_ACTIVE(tm->bus_act_mask, bus_index); in ddr3_tip_bus_read()
1181 VALIDATE_ACTIVE(tm->bus_act_mask, bus_cnt); in adll_calibration()
1304 VALIDATE_ACTIVE(tm->bus_act_mask, bus_index); in ddr3_tip_freq_set()
1433 VALIDATE_ACTIVE(tm->bus_act_mask, bus_cnt); in ddr3_tip_freq_set()
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H A Dddr_topology_def.h109 u8 bus_act_mask; member
H A Dddr3_training_db.c533 if (DDR3_IS_16BIT_DRAM_MODE(tm->bus_act_mask) == 0) { in pattern_table_get_word()
H A Dddr3_a38x.c722 if (DDR3_IS_16BIT_DRAM_MODE(tm->bus_act_mask)) { in ddr3_silicon_post_init()