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Searched refs:ahb_reset1_cfg (Results 1 – 7 of 7) sorted by relevance

/OK3568_Linux_fs/u-boot/drivers/video/sunxi/
H A Dsunxi_dw_hdmi.c255 setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_LCD0); in sunxi_dw_hdmi_lcdc_init()
265 setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_LCD1); in sunxi_dw_hdmi_lcdc_init()
346 setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_HDMI); in sunxi_dw_hdmi_probe()
347 setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_HDMI2); in sunxi_dw_hdmi_probe()
H A Dsunxi_display.c105 setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_HDMI); in sunxi_hdmi_hpd_detect()
134 clrbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_HDMI); in sunxi_hdmi_shutdown()
445 setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_DE_BE0); in sunxi_composer_init()
640 setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_LCD0); in sunxi_lcdc_init()
965 setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_SAT);
967 setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_DRC0);
H A Dsunxi_de2.c51 setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_DE); in sunxi_de2_composer_init()
/OK3568_Linux_fs/u-boot/arch/arm/mach-sunxi/
H A Dclock_sun9i.c62 setbits_le32(&ccm->ahb_reset1_cfg, (1 << 24)); in clock_init_safe()
/OK3568_Linux_fs/u-boot/arch/arm/include/asm/arch-sunxi/
H A Dclock_sun9i.h92 u32 ahb_reset1_cfg; /* 0x5a4 AHB1 Software Reset Register */ member
H A Dclock_sun8i_a83t.h121 u32 ahb_reset1_cfg; /* 0x2c4 AHB1 Reset 1 config */ member
H A Dclock_sun6i.h152 u32 ahb_reset1_cfg; /* 0x2c4 AHB1 Reset 1 config */ member