Searched refs:__bf_shf (Results 1 – 15 of 15) sorted by relevance
49 #define __bf_shf(x) (__builtin_ffsll(x) - 1) macro57 ~((_mask) >> __bf_shf(_mask)) & (_val) : 0, \62 (1ULL << __bf_shf(_mask))); \75 !((((typeof(_mask))_val) << __bf_shf(_mask)) & ~(_mask)); \89 ((typeof(_mask))(_val) << __bf_shf(_mask)) & (_mask); \103 (typeof(_mask))(((_reg) & (_mask)) >> __bf_shf(_mask)); \
42 #define __bf_shf(x) (__builtin_ffsll(x) - 1) macro66 ~((_mask) >> __bf_shf(_mask)) & (_val) : 0, \72 (1ULL << __bf_shf(_mask))); \85 (typeof(_mask))((_mask) >> __bf_shf(_mask)); \98 !((((typeof(_mask))_val) << __bf_shf(_mask)) & ~(_mask)); \112 ((typeof(_mask))(_val) << __bf_shf(_mask)) & (_mask); \126 (typeof(_mask))(((_reg) & (_mask)) >> __bf_shf(_mask)); \
62 int bit = __bf_shf(MV88E6352_G1_STS_PPU_STATE); in mv88e6352_g1_wait_ppu_polling()69 int bit = __bf_shf(MV88E6XXX_G1_STS_INIT_READY); in mv88e6xxx_g1_wait_init_ready()333 __bf_shf(MV88E6185_G1_MONITOR_CTL_INGRESS_DEST_MASK); in mv88e6095_g1_set_egress_port()339 __bf_shf(MV88E6185_G1_MONITOR_CTL_EGRESS_DEST_MASK); in mv88e6095_g1_set_egress_port()366 reg |= port << __bf_shf(MV88E6185_G1_MONITOR_CTL_ARP_DEST_MASK); in mv88e6095_g1_set_cpu_port()475 return mv88e6xxx_g1_ctl2_mask(chip, mask, port << __bf_shf(mask)); in mv88e6185_g1_set_cascade_port()514 int bit = __bf_shf(MV88E6XXX_G1_STATS_OP_BUSY); in mv88e6xxx_g1_stats_wait()
1167 (ptr << __bf_shf(MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_PTR_MASK)) | in mv88e6xxx_port_ieeepmt_write()1217 shift = __bf_shf(MV88E6XXX_PORT_POLICY_CTL_DA_MASK); in mv88e6352_port_set_policy()1221 shift = __bf_shf(MV88E6XXX_PORT_POLICY_CTL_SA_MASK); in mv88e6352_port_set_policy()1225 shift = __bf_shf(MV88E6XXX_PORT_POLICY_CTL_VTU_MASK); in mv88e6352_port_set_policy()1229 shift = __bf_shf(MV88E6XXX_PORT_POLICY_CTL_ETYPE_MASK); in mv88e6352_port_set_policy()1233 shift = __bf_shf(MV88E6XXX_PORT_POLICY_CTL_PPPOE_MASK); in mv88e6352_port_set_policy()1237 shift = __bf_shf(MV88E6XXX_PORT_POLICY_CTL_VBAS_MASK); in mv88e6352_port_set_policy()1241 shift = __bf_shf(MV88E6XXX_PORT_POLICY_CTL_OPT82_MASK); in mv88e6352_port_set_policy()1245 shift = __bf_shf(MV88E6XXX_PORT_POLICY_CTL_UDP_MASK); in mv88e6352_port_set_policy()
181 int bit = __bf_shf(MV88E6XXX_G2_IRL_CMD_BUSY); in mv88e6xxx_g2_irl_wait()218 int bit = __bf_shf(MV88E6XXX_G2_PVT_ADDR_BUSY); in mv88e6xxx_g2_pvt_op_wait()328 int bit = __bf_shf(MV88E6XXX_G2_EEPROM_CMD_BUSY); in mv88e6xxx_g2_eeprom_wait()335 bit = __bf_shf(MV88E6XXX_G2_EEPROM_CMD_RUNNING); in mv88e6xxx_g2_eeprom_wait()599 int bit = __bf_shf(MV88E6XXX_G2_SMI_PHY_CMD_BUSY); in mv88e6xxx_g2_smi_phy_wait()632 dev <<= __bf_shf(MV88E6XXX_G2_SMI_PHY_CMD_DEV_ADDR_MASK); in mv88e6xxx_g2_smi_phy_access()
41 int bit = __bf_shf(MV88E6XXX_PORT_RESERVED_1A_BUSY); in mv88e6xxx_port_hidden_wait()
34 int bit = __bf_shf(MV88E6352_G2_AVB_CMD_BUSY); in mv88e6xxx_g2_avb_wait()
112 int bit = __bf_shf(MV88E6XXX_G1_ATU_OP_BUSY); in mv88e6xxx_g1_atu_op_wait()
71 int bit = __bf_shf(MV88E6XXX_G1_VTU_OP_BUSY); in mv88e6xxx_g1_vtu_op_wait()
37 return (addr_hi * ((OP_BR_ADDR_LO >> __bf_shf(OP_BR_ADDR_LO)) + 1)) | in br_get_offset()45 addr_lo = offset & (OP_BR_ADDR_LO >> __bf_shf(OP_BR_ADDR_LO)); in br_set_offset()
25 #define __bf_shf(x) (__builtin_ffsll(x) - 1) macro37 ((typeof(_mask))(_val) << __bf_shf(_mask)) & (_mask); \
498 nfp_eth_set_bit_config(nsp, raw_idx, mask, __bf_shf(mask), \
147 addr_lo = addr & (OP_BR_ADDR_LO >> __bf_shf(OP_BR_ADDR_LO)); in __emit_br()192 addr_lo = addr & (OP_BR_BIT_ADDR_LO >> __bf_shf(OP_BR_BIT_ADDR_LO)); in __emit_br_bit()
163 ((u32)((((typeof(__mask))(__val) << __bf_shf(__mask)) & (__mask)) + \166 BUILD_BUG_ON_ZERO(!IS_POWER_OF_2((__mask) + (1ULL << __bf_shf(__mask)))) + \167 …BUILD_BUG_ON_ZERO(__builtin_choose_expr(__is_constexpr(__val), (~((__mask) >> __bf_shf(__mask)) & …