Searched refs:SCLK_I2S0_DIV (Results 1 – 3 of 3) sorted by relevance
52 assigned-clocks = <&cru SCLK_I2S0_DIV>;
134 #define SCLK_I2S0_DIV 174 macro
677 COMPOSITE(SCLK_I2S0_DIV, "clk_i2s0_div", mux_pll_src_cpll_gpll_p, 0,