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Searched refs:RADEON_CRTC2_GEN_CNTL (Results 1 – 7 of 7) sorted by relevance

/OK3568_Linux_fs/kernel/drivers/gpu/drm/radeon/
H A Dradeon_legacy_encoders.c1056 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL); in radeon_legacy_tv_dac_dpms()
1118 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl); in radeon_legacy_tv_dac_dpms()
1318 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL); in r300_legacy_tv_detect()
1327 WREG32(RADEON_CRTC2_GEN_CNTL, in r300_legacy_tv_detect()
1370 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl); in r300_legacy_tv_detect()
1458 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL); in radeon_legacy_ext_dac_detect()
1483 WREG32(RADEON_CRTC2_GEN_CNTL, (RADEON_CRTC2_EN | in radeon_legacy_ext_dac_detect()
1523 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl); in radeon_legacy_ext_dac_detect()
1594 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL); in radeon_legacy_tv_dac_detect()
1611 WREG32(RADEON_CRTC2_GEN_CNTL, tmp); in radeon_legacy_tv_dac_detect()
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H A Dradeon_legacy_crtc.c331 WREG32_P(RADEON_CRTC2_GEN_CNTL, RADEON_CRTC2_EN, ~(RADEON_CRTC2_EN | mask)); in radeon_crtc_dpms()
347 WREG32_P(RADEON_CRTC2_GEN_CNTL, mask, ~(RADEON_CRTC2_EN | mask)); in radeon_crtc_dpms()
534 gen_cntl_reg = RADEON_CRTC2_GEN_CNTL; in radeon_crtc_do_set_base()
655 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL) & 0x00718080; in radeon_set_crtc_timing()
679 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl); in radeon_set_crtc_timing()
H A Dradeon_bios.c536 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL); in legacy_read_disabled_bios()
558 WREG32(RADEON_CRTC2_GEN_CNTL, in legacy_read_disabled_bios()
583 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl); in legacy_read_disabled_bios()
H A Dradeon_cursor.c81 reg = RADEON_CRTC2_GEN_CNTL; in radeon_hide_cursor()
132 WREG32(RADEON_MM_INDEX, RADEON_CRTC2_GEN_CNTL); in radeon_show_cursor()
H A Dr100.c128 if (!(RREG32(RADEON_CRTC2_GEN_CNTL) & RADEON_CRTC2_EN)) in r100_wait_for_vblank()
461 tmp = RREG32(RADEON_CRTC2_GEN_CNTL); in r100_pm_prepare()
463 WREG32(RADEON_CRTC2_GEN_CNTL, tmp); in r100_pm_prepare()
492 tmp = RREG32(RADEON_CRTC2_GEN_CNTL); in r100_pm_finish()
494 WREG32(RADEON_CRTC2_GEN_CNTL, tmp); in r100_pm_finish()
H A Dradeon_device.c695 RREG32(RADEON_CRTC2_GEN_CNTL); in radeon_card_posted()
H A Dradeon_reg.h449 #define RADEON_CRTC2_GEN_CNTL 0x03f8 macro