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Searched refs:PP_CONTROL (Results 1 – 12 of 12) sorted by relevance

/OK3568_Linux_fs/kernel/drivers/gpu/drm/gma500/
H A Dpsb_lid.c28 REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) | POWER_TARGET_ON); in psb_lid_timer_func()
44 REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) & ~POWER_TARGET_ON); in psb_lid_timer_func()
H A Dpsb_intel_lvds.c221 REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) | in psb_intel_lvds_set_power()
232 REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) & in psb_intel_lvds_set_power()
266 lvds_priv->savePP_CONTROL = REG_READ(PP_CONTROL); in psb_intel_lvds_save()
317 REG_WRITE(PP_CONTROL, lvds_priv->savePP_CONTROL); in psb_intel_lvds_restore()
321 REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) | in psb_intel_lvds_restore()
327 REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) & in psb_intel_lvds_restore()
H A Dcdv_intel_dp.c392 pp = REG_READ(PP_CONTROL); in cdv_intel_edp_panel_vdd_on()
395 REG_WRITE(PP_CONTROL, pp); in cdv_intel_edp_panel_vdd_on()
396 REG_READ(PP_CONTROL); in cdv_intel_edp_panel_vdd_on()
406 pp = REG_READ(PP_CONTROL); in cdv_intel_edp_panel_vdd_off()
409 REG_WRITE(PP_CONTROL, pp); in cdv_intel_edp_panel_vdd_off()
410 REG_READ(PP_CONTROL); in cdv_intel_edp_panel_vdd_off()
425 pp = REG_READ(PP_CONTROL); in cdv_intel_edp_panel_on()
429 REG_WRITE(PP_CONTROL, pp); in cdv_intel_edp_panel_on()
430 REG_READ(PP_CONTROL); in cdv_intel_edp_panel_on()
450 pp = REG_READ(PP_CONTROL); in cdv_intel_edp_panel_off()
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H A Doaktrail_lvds.c46 REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) | in oaktrail_lvds_set_power()
57 REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) & in oaktrail_lvds_set_power()
H A Dcdv_intel_lvds.c115 REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) | in cdv_intel_lvds_set_power()
126 REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) & in cdv_intel_lvds_set_power()
H A Doaktrail_device.c233 regs->psb.savePP_CONTROL = PSB_RVDC32(PP_CONTROL); in oaktrail_save_display_registers()
262 PSB_WVDC32(0, PP_CONTROL); in oaktrail_save_display_registers()
370 PSB_WVDC32(regs->psb.savePP_CONTROL, PP_CONTROL); in oaktrail_restore_display_registers()
H A Dcdv_device.c278 regs->cdv.savePP_CONTROL = REG_READ(PP_CONTROL); in cdv_save_display_registers()
357 REG_WRITE(PP_CONTROL, regs->cdv.savePP_CONTROL); in cdv_restore_display_registers()
H A Dpsb_intel_reg.h168 #define PP_CONTROL 0x61204 macro
/OK3568_Linux_fs/kernel/drivers/gpu/drm/i915/display/
H A Dintel_lvds.c158 pps->powerdown_on_reset = intel_de_read(dev_priv, PP_CONTROL(0)) & PANEL_POWER_RESET; in intel_lvds_pps_get_hw_state()
206 val = intel_de_read(dev_priv, PP_CONTROL(0)); in intel_lvds_pps_init_hw()
211 intel_de_write(dev_priv, PP_CONTROL(0), val); in intel_lvds_pps_init_hw()
317 intel_de_write(dev_priv, PP_CONTROL(0), in intel_enable_lvds()
318 intel_de_read(dev_priv, PP_CONTROL(0)) | PANEL_POWER_ON); in intel_enable_lvds()
336 intel_de_write(dev_priv, PP_CONTROL(0), in intel_disable_lvds()
337 intel_de_read(dev_priv, PP_CONTROL(0)) & ~PANEL_POWER_ON); in intel_disable_lvds()
H A Dintel_dp.c990 return intel_de_read(dev_priv, PP_CONTROL(pipe)) & EDP_FORCE_VDD; in vlv_pipe_has_vdd_on()
1120 regs->pp_ctrl = PP_CONTROL(pps_idx); in intel_pps_get_registers()
1171 pp_ctrl_reg = PP_CONTROL(pipe); in edp_notify_handler()
H A Dintel_display.c1221 pp_reg = PP_CONTROL(0); in assert_panel_unlocked()
1243 pp_reg = PP_CONTROL(pipe); in assert_panel_unlocked()
1248 pp_reg = PP_CONTROL(0); in assert_panel_unlocked()
16865 u32 val = intel_de_read(dev_priv, PP_CONTROL(pps_idx)); in intel_pps_unlock_regs_wa()
16868 intel_de_write(dev_priv, PP_CONTROL(pps_idx), val); in intel_pps_unlock_regs_wa()
/OK3568_Linux_fs/kernel/drivers/gpu/drm/i915/
H A Di915_reg.h5031 #define PP_CONTROL(pps_idx) _MMIO_PPS(pps_idx, _PP_CONTROL) macro