1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright © 2006-2009 Intel Corporation
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Authors:
6*4882a593Smuzhiyun * Eric Anholt <eric@anholt.net>
7*4882a593Smuzhiyun * Dave Airlie <airlied@linux.ie>
8*4882a593Smuzhiyun * Jesse Barnes <jesse.barnes@intel.com>
9*4882a593Smuzhiyun */
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun #include <linux/i2c.h>
12*4882a593Smuzhiyun #include <linux/pm_runtime.h>
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun #include <asm/intel-mid.h>
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun #include <drm/drm_simple_kms_helper.h>
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun #include "intel_bios.h"
19*4882a593Smuzhiyun #include "power.h"
20*4882a593Smuzhiyun #include "psb_drv.h"
21*4882a593Smuzhiyun #include "psb_intel_drv.h"
22*4882a593Smuzhiyun #include "psb_intel_reg.h"
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun /* The max/min PWM frequency in BPCR[31:17] - */
25*4882a593Smuzhiyun /* The smallest number is 1 (not 0) that can fit in the
26*4882a593Smuzhiyun * 15-bit field of the and then*/
27*4882a593Smuzhiyun /* shifts to the left by one bit to get the actual 16-bit
28*4882a593Smuzhiyun * value that the 15-bits correspond to.*/
29*4882a593Smuzhiyun #define MRST_BLC_MAX_PWM_REG_FREQ 0xFFFF
30*4882a593Smuzhiyun #define BRIGHTNESS_MAX_LEVEL 100
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun /**
33*4882a593Smuzhiyun * Sets the power state for the panel.
34*4882a593Smuzhiyun */
oaktrail_lvds_set_power(struct drm_device * dev,struct gma_encoder * gma_encoder,bool on)35*4882a593Smuzhiyun static void oaktrail_lvds_set_power(struct drm_device *dev,
36*4882a593Smuzhiyun struct gma_encoder *gma_encoder,
37*4882a593Smuzhiyun bool on)
38*4882a593Smuzhiyun {
39*4882a593Smuzhiyun u32 pp_status;
40*4882a593Smuzhiyun struct drm_psb_private *dev_priv = dev->dev_private;
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun if (!gma_power_begin(dev, true))
43*4882a593Smuzhiyun return;
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun if (on) {
46*4882a593Smuzhiyun REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) |
47*4882a593Smuzhiyun POWER_TARGET_ON);
48*4882a593Smuzhiyun do {
49*4882a593Smuzhiyun pp_status = REG_READ(PP_STATUS);
50*4882a593Smuzhiyun } while ((pp_status & (PP_ON | PP_READY)) == PP_READY);
51*4882a593Smuzhiyun dev_priv->is_lvds_on = true;
52*4882a593Smuzhiyun if (dev_priv->ops->lvds_bl_power)
53*4882a593Smuzhiyun dev_priv->ops->lvds_bl_power(dev, true);
54*4882a593Smuzhiyun } else {
55*4882a593Smuzhiyun if (dev_priv->ops->lvds_bl_power)
56*4882a593Smuzhiyun dev_priv->ops->lvds_bl_power(dev, false);
57*4882a593Smuzhiyun REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) &
58*4882a593Smuzhiyun ~POWER_TARGET_ON);
59*4882a593Smuzhiyun do {
60*4882a593Smuzhiyun pp_status = REG_READ(PP_STATUS);
61*4882a593Smuzhiyun } while (pp_status & PP_ON);
62*4882a593Smuzhiyun dev_priv->is_lvds_on = false;
63*4882a593Smuzhiyun pm_request_idle(&dev->pdev->dev);
64*4882a593Smuzhiyun }
65*4882a593Smuzhiyun gma_power_end(dev);
66*4882a593Smuzhiyun }
67*4882a593Smuzhiyun
oaktrail_lvds_dpms(struct drm_encoder * encoder,int mode)68*4882a593Smuzhiyun static void oaktrail_lvds_dpms(struct drm_encoder *encoder, int mode)
69*4882a593Smuzhiyun {
70*4882a593Smuzhiyun struct drm_device *dev = encoder->dev;
71*4882a593Smuzhiyun struct gma_encoder *gma_encoder = to_gma_encoder(encoder);
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun if (mode == DRM_MODE_DPMS_ON)
74*4882a593Smuzhiyun oaktrail_lvds_set_power(dev, gma_encoder, true);
75*4882a593Smuzhiyun else
76*4882a593Smuzhiyun oaktrail_lvds_set_power(dev, gma_encoder, false);
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun /* XXX: We never power down the LVDS pairs. */
79*4882a593Smuzhiyun }
80*4882a593Smuzhiyun
oaktrail_lvds_mode_set(struct drm_encoder * encoder,struct drm_display_mode * mode,struct drm_display_mode * adjusted_mode)81*4882a593Smuzhiyun static void oaktrail_lvds_mode_set(struct drm_encoder *encoder,
82*4882a593Smuzhiyun struct drm_display_mode *mode,
83*4882a593Smuzhiyun struct drm_display_mode *adjusted_mode)
84*4882a593Smuzhiyun {
85*4882a593Smuzhiyun struct drm_device *dev = encoder->dev;
86*4882a593Smuzhiyun struct drm_psb_private *dev_priv = dev->dev_private;
87*4882a593Smuzhiyun struct psb_intel_mode_device *mode_dev = &dev_priv->mode_dev;
88*4882a593Smuzhiyun struct drm_mode_config *mode_config = &dev->mode_config;
89*4882a593Smuzhiyun struct drm_connector *connector = NULL;
90*4882a593Smuzhiyun struct drm_crtc *crtc = encoder->crtc;
91*4882a593Smuzhiyun u32 lvds_port;
92*4882a593Smuzhiyun uint64_t v = DRM_MODE_SCALE_FULLSCREEN;
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun if (!gma_power_begin(dev, true))
95*4882a593Smuzhiyun return;
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun /*
98*4882a593Smuzhiyun * The LVDS pin pair will already have been turned on in the
99*4882a593Smuzhiyun * psb_intel_crtc_mode_set since it has a large impact on the DPLL
100*4882a593Smuzhiyun * settings.
101*4882a593Smuzhiyun */
102*4882a593Smuzhiyun lvds_port = (REG_READ(LVDS) &
103*4882a593Smuzhiyun (~LVDS_PIPEB_SELECT)) |
104*4882a593Smuzhiyun LVDS_PORT_EN |
105*4882a593Smuzhiyun LVDS_BORDER_EN;
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun /* If the firmware says dither on Moorestown, or the BIOS does
108*4882a593Smuzhiyun on Oaktrail then enable dithering */
109*4882a593Smuzhiyun if (mode_dev->panel_wants_dither || dev_priv->lvds_dither)
110*4882a593Smuzhiyun lvds_port |= MRST_PANEL_8TO6_DITHER_ENABLE;
111*4882a593Smuzhiyun
112*4882a593Smuzhiyun REG_WRITE(LVDS, lvds_port);
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun /* Find the connector we're trying to set up */
115*4882a593Smuzhiyun list_for_each_entry(connector, &mode_config->connector_list, head) {
116*4882a593Smuzhiyun if (!connector->encoder || connector->encoder->crtc != crtc)
117*4882a593Smuzhiyun continue;
118*4882a593Smuzhiyun }
119*4882a593Smuzhiyun
120*4882a593Smuzhiyun if (list_entry_is_head(connector, &mode_config->connector_list, head)) {
121*4882a593Smuzhiyun DRM_ERROR("Couldn't find connector when setting mode");
122*4882a593Smuzhiyun gma_power_end(dev);
123*4882a593Smuzhiyun return;
124*4882a593Smuzhiyun }
125*4882a593Smuzhiyun
126*4882a593Smuzhiyun drm_object_property_get_value(
127*4882a593Smuzhiyun &connector->base,
128*4882a593Smuzhiyun dev->mode_config.scaling_mode_property,
129*4882a593Smuzhiyun &v);
130*4882a593Smuzhiyun
131*4882a593Smuzhiyun if (v == DRM_MODE_SCALE_NO_SCALE)
132*4882a593Smuzhiyun REG_WRITE(PFIT_CONTROL, 0);
133*4882a593Smuzhiyun else if (v == DRM_MODE_SCALE_ASPECT) {
134*4882a593Smuzhiyun if ((mode->vdisplay != adjusted_mode->crtc_vdisplay) ||
135*4882a593Smuzhiyun (mode->hdisplay != adjusted_mode->crtc_hdisplay)) {
136*4882a593Smuzhiyun if ((adjusted_mode->crtc_hdisplay * mode->vdisplay) ==
137*4882a593Smuzhiyun (mode->hdisplay * adjusted_mode->crtc_vdisplay))
138*4882a593Smuzhiyun REG_WRITE(PFIT_CONTROL, PFIT_ENABLE);
139*4882a593Smuzhiyun else if ((adjusted_mode->crtc_hdisplay *
140*4882a593Smuzhiyun mode->vdisplay) > (mode->hdisplay *
141*4882a593Smuzhiyun adjusted_mode->crtc_vdisplay))
142*4882a593Smuzhiyun REG_WRITE(PFIT_CONTROL, PFIT_ENABLE |
143*4882a593Smuzhiyun PFIT_SCALING_MODE_PILLARBOX);
144*4882a593Smuzhiyun else
145*4882a593Smuzhiyun REG_WRITE(PFIT_CONTROL, PFIT_ENABLE |
146*4882a593Smuzhiyun PFIT_SCALING_MODE_LETTERBOX);
147*4882a593Smuzhiyun } else
148*4882a593Smuzhiyun REG_WRITE(PFIT_CONTROL, PFIT_ENABLE);
149*4882a593Smuzhiyun } else /*(v == DRM_MODE_SCALE_FULLSCREEN)*/
150*4882a593Smuzhiyun REG_WRITE(PFIT_CONTROL, PFIT_ENABLE);
151*4882a593Smuzhiyun
152*4882a593Smuzhiyun gma_power_end(dev);
153*4882a593Smuzhiyun }
154*4882a593Smuzhiyun
oaktrail_lvds_prepare(struct drm_encoder * encoder)155*4882a593Smuzhiyun static void oaktrail_lvds_prepare(struct drm_encoder *encoder)
156*4882a593Smuzhiyun {
157*4882a593Smuzhiyun struct drm_device *dev = encoder->dev;
158*4882a593Smuzhiyun struct drm_psb_private *dev_priv = dev->dev_private;
159*4882a593Smuzhiyun struct gma_encoder *gma_encoder = to_gma_encoder(encoder);
160*4882a593Smuzhiyun struct psb_intel_mode_device *mode_dev = &dev_priv->mode_dev;
161*4882a593Smuzhiyun
162*4882a593Smuzhiyun if (!gma_power_begin(dev, true))
163*4882a593Smuzhiyun return;
164*4882a593Smuzhiyun
165*4882a593Smuzhiyun mode_dev->saveBLC_PWM_CTL = REG_READ(BLC_PWM_CTL);
166*4882a593Smuzhiyun mode_dev->backlight_duty_cycle = (mode_dev->saveBLC_PWM_CTL &
167*4882a593Smuzhiyun BACKLIGHT_DUTY_CYCLE_MASK);
168*4882a593Smuzhiyun oaktrail_lvds_set_power(dev, gma_encoder, false);
169*4882a593Smuzhiyun gma_power_end(dev);
170*4882a593Smuzhiyun }
171*4882a593Smuzhiyun
oaktrail_lvds_get_max_backlight(struct drm_device * dev)172*4882a593Smuzhiyun static u32 oaktrail_lvds_get_max_backlight(struct drm_device *dev)
173*4882a593Smuzhiyun {
174*4882a593Smuzhiyun struct drm_psb_private *dev_priv = dev->dev_private;
175*4882a593Smuzhiyun u32 ret;
176*4882a593Smuzhiyun
177*4882a593Smuzhiyun if (gma_power_begin(dev, false)) {
178*4882a593Smuzhiyun ret = ((REG_READ(BLC_PWM_CTL) &
179*4882a593Smuzhiyun BACKLIGHT_MODULATION_FREQ_MASK) >>
180*4882a593Smuzhiyun BACKLIGHT_MODULATION_FREQ_SHIFT) * 2;
181*4882a593Smuzhiyun
182*4882a593Smuzhiyun gma_power_end(dev);
183*4882a593Smuzhiyun } else
184*4882a593Smuzhiyun ret = ((dev_priv->regs.saveBLC_PWM_CTL &
185*4882a593Smuzhiyun BACKLIGHT_MODULATION_FREQ_MASK) >>
186*4882a593Smuzhiyun BACKLIGHT_MODULATION_FREQ_SHIFT) * 2;
187*4882a593Smuzhiyun
188*4882a593Smuzhiyun return ret;
189*4882a593Smuzhiyun }
190*4882a593Smuzhiyun
oaktrail_lvds_commit(struct drm_encoder * encoder)191*4882a593Smuzhiyun static void oaktrail_lvds_commit(struct drm_encoder *encoder)
192*4882a593Smuzhiyun {
193*4882a593Smuzhiyun struct drm_device *dev = encoder->dev;
194*4882a593Smuzhiyun struct drm_psb_private *dev_priv = dev->dev_private;
195*4882a593Smuzhiyun struct gma_encoder *gma_encoder = to_gma_encoder(encoder);
196*4882a593Smuzhiyun struct psb_intel_mode_device *mode_dev = &dev_priv->mode_dev;
197*4882a593Smuzhiyun
198*4882a593Smuzhiyun if (mode_dev->backlight_duty_cycle == 0)
199*4882a593Smuzhiyun mode_dev->backlight_duty_cycle =
200*4882a593Smuzhiyun oaktrail_lvds_get_max_backlight(dev);
201*4882a593Smuzhiyun oaktrail_lvds_set_power(dev, gma_encoder, true);
202*4882a593Smuzhiyun }
203*4882a593Smuzhiyun
204*4882a593Smuzhiyun static const struct drm_encoder_helper_funcs oaktrail_lvds_helper_funcs = {
205*4882a593Smuzhiyun .dpms = oaktrail_lvds_dpms,
206*4882a593Smuzhiyun .mode_fixup = psb_intel_lvds_mode_fixup,
207*4882a593Smuzhiyun .prepare = oaktrail_lvds_prepare,
208*4882a593Smuzhiyun .mode_set = oaktrail_lvds_mode_set,
209*4882a593Smuzhiyun .commit = oaktrail_lvds_commit,
210*4882a593Smuzhiyun };
211*4882a593Smuzhiyun
212*4882a593Smuzhiyun /* Returns the panel fixed mode from configuration. */
213*4882a593Smuzhiyun
oaktrail_lvds_get_configuration_mode(struct drm_device * dev,struct psb_intel_mode_device * mode_dev)214*4882a593Smuzhiyun static void oaktrail_lvds_get_configuration_mode(struct drm_device *dev,
215*4882a593Smuzhiyun struct psb_intel_mode_device *mode_dev)
216*4882a593Smuzhiyun {
217*4882a593Smuzhiyun struct drm_display_mode *mode = NULL;
218*4882a593Smuzhiyun struct drm_psb_private *dev_priv = dev->dev_private;
219*4882a593Smuzhiyun struct oaktrail_timing_info *ti = &dev_priv->gct_data.DTD;
220*4882a593Smuzhiyun
221*4882a593Smuzhiyun mode_dev->panel_fixed_mode = NULL;
222*4882a593Smuzhiyun
223*4882a593Smuzhiyun /* Use the firmware provided data on Moorestown */
224*4882a593Smuzhiyun if (dev_priv->has_gct) {
225*4882a593Smuzhiyun mode = kzalloc(sizeof(*mode), GFP_KERNEL);
226*4882a593Smuzhiyun if (!mode)
227*4882a593Smuzhiyun return;
228*4882a593Smuzhiyun
229*4882a593Smuzhiyun mode->hdisplay = (ti->hactive_hi << 8) | ti->hactive_lo;
230*4882a593Smuzhiyun mode->vdisplay = (ti->vactive_hi << 8) | ti->vactive_lo;
231*4882a593Smuzhiyun mode->hsync_start = mode->hdisplay + \
232*4882a593Smuzhiyun ((ti->hsync_offset_hi << 8) | \
233*4882a593Smuzhiyun ti->hsync_offset_lo);
234*4882a593Smuzhiyun mode->hsync_end = mode->hsync_start + \
235*4882a593Smuzhiyun ((ti->hsync_pulse_width_hi << 8) | \
236*4882a593Smuzhiyun ti->hsync_pulse_width_lo);
237*4882a593Smuzhiyun mode->htotal = mode->hdisplay + ((ti->hblank_hi << 8) | \
238*4882a593Smuzhiyun ti->hblank_lo);
239*4882a593Smuzhiyun mode->vsync_start = \
240*4882a593Smuzhiyun mode->vdisplay + ((ti->vsync_offset_hi << 4) | \
241*4882a593Smuzhiyun ti->vsync_offset_lo);
242*4882a593Smuzhiyun mode->vsync_end = \
243*4882a593Smuzhiyun mode->vsync_start + ((ti->vsync_pulse_width_hi << 4) | \
244*4882a593Smuzhiyun ti->vsync_pulse_width_lo);
245*4882a593Smuzhiyun mode->vtotal = mode->vdisplay + \
246*4882a593Smuzhiyun ((ti->vblank_hi << 8) | ti->vblank_lo);
247*4882a593Smuzhiyun mode->clock = ti->pixel_clock * 10;
248*4882a593Smuzhiyun #if 0
249*4882a593Smuzhiyun pr_info("hdisplay is %d\n", mode->hdisplay);
250*4882a593Smuzhiyun pr_info("vdisplay is %d\n", mode->vdisplay);
251*4882a593Smuzhiyun pr_info("HSS is %d\n", mode->hsync_start);
252*4882a593Smuzhiyun pr_info("HSE is %d\n", mode->hsync_end);
253*4882a593Smuzhiyun pr_info("htotal is %d\n", mode->htotal);
254*4882a593Smuzhiyun pr_info("VSS is %d\n", mode->vsync_start);
255*4882a593Smuzhiyun pr_info("VSE is %d\n", mode->vsync_end);
256*4882a593Smuzhiyun pr_info("vtotal is %d\n", mode->vtotal);
257*4882a593Smuzhiyun pr_info("clock is %d\n", mode->clock);
258*4882a593Smuzhiyun #endif
259*4882a593Smuzhiyun mode_dev->panel_fixed_mode = mode;
260*4882a593Smuzhiyun }
261*4882a593Smuzhiyun
262*4882a593Smuzhiyun /* Use the BIOS VBT mode if available */
263*4882a593Smuzhiyun if (mode_dev->panel_fixed_mode == NULL && mode_dev->vbt_mode)
264*4882a593Smuzhiyun mode_dev->panel_fixed_mode = drm_mode_duplicate(dev,
265*4882a593Smuzhiyun mode_dev->vbt_mode);
266*4882a593Smuzhiyun
267*4882a593Smuzhiyun /* Then try the LVDS VBT mode */
268*4882a593Smuzhiyun if (mode_dev->panel_fixed_mode == NULL)
269*4882a593Smuzhiyun if (dev_priv->lfp_lvds_vbt_mode)
270*4882a593Smuzhiyun mode_dev->panel_fixed_mode =
271*4882a593Smuzhiyun drm_mode_duplicate(dev,
272*4882a593Smuzhiyun dev_priv->lfp_lvds_vbt_mode);
273*4882a593Smuzhiyun
274*4882a593Smuzhiyun /* If we still got no mode then bail */
275*4882a593Smuzhiyun if (mode_dev->panel_fixed_mode == NULL)
276*4882a593Smuzhiyun return;
277*4882a593Smuzhiyun
278*4882a593Smuzhiyun drm_mode_set_name(mode_dev->panel_fixed_mode);
279*4882a593Smuzhiyun drm_mode_set_crtcinfo(mode_dev->panel_fixed_mode, 0);
280*4882a593Smuzhiyun }
281*4882a593Smuzhiyun
282*4882a593Smuzhiyun /**
283*4882a593Smuzhiyun * oaktrail_lvds_init - setup LVDS connectors on this device
284*4882a593Smuzhiyun * @dev: drm device
285*4882a593Smuzhiyun *
286*4882a593Smuzhiyun * Create the connector, register the LVDS DDC bus, and try to figure out what
287*4882a593Smuzhiyun * modes we can display on the LVDS panel (if present).
288*4882a593Smuzhiyun */
oaktrail_lvds_init(struct drm_device * dev,struct psb_intel_mode_device * mode_dev)289*4882a593Smuzhiyun void oaktrail_lvds_init(struct drm_device *dev,
290*4882a593Smuzhiyun struct psb_intel_mode_device *mode_dev)
291*4882a593Smuzhiyun {
292*4882a593Smuzhiyun struct gma_encoder *gma_encoder;
293*4882a593Smuzhiyun struct gma_connector *gma_connector;
294*4882a593Smuzhiyun struct drm_connector *connector;
295*4882a593Smuzhiyun struct drm_encoder *encoder;
296*4882a593Smuzhiyun struct drm_psb_private *dev_priv = dev->dev_private;
297*4882a593Smuzhiyun struct edid *edid;
298*4882a593Smuzhiyun struct i2c_adapter *i2c_adap;
299*4882a593Smuzhiyun struct drm_display_mode *scan; /* *modes, *bios_mode; */
300*4882a593Smuzhiyun
301*4882a593Smuzhiyun gma_encoder = kzalloc(sizeof(struct gma_encoder), GFP_KERNEL);
302*4882a593Smuzhiyun if (!gma_encoder)
303*4882a593Smuzhiyun return;
304*4882a593Smuzhiyun
305*4882a593Smuzhiyun gma_connector = kzalloc(sizeof(struct gma_connector), GFP_KERNEL);
306*4882a593Smuzhiyun if (!gma_connector)
307*4882a593Smuzhiyun goto failed_connector;
308*4882a593Smuzhiyun
309*4882a593Smuzhiyun connector = &gma_connector->base;
310*4882a593Smuzhiyun encoder = &gma_encoder->base;
311*4882a593Smuzhiyun dev_priv->is_lvds_on = true;
312*4882a593Smuzhiyun drm_connector_init(dev, connector,
313*4882a593Smuzhiyun &psb_intel_lvds_connector_funcs,
314*4882a593Smuzhiyun DRM_MODE_CONNECTOR_LVDS);
315*4882a593Smuzhiyun
316*4882a593Smuzhiyun drm_simple_encoder_init(dev, encoder, DRM_MODE_ENCODER_LVDS);
317*4882a593Smuzhiyun
318*4882a593Smuzhiyun gma_connector_attach_encoder(gma_connector, gma_encoder);
319*4882a593Smuzhiyun gma_encoder->type = INTEL_OUTPUT_LVDS;
320*4882a593Smuzhiyun
321*4882a593Smuzhiyun drm_encoder_helper_add(encoder, &oaktrail_lvds_helper_funcs);
322*4882a593Smuzhiyun drm_connector_helper_add(connector,
323*4882a593Smuzhiyun &psb_intel_lvds_connector_helper_funcs);
324*4882a593Smuzhiyun connector->display_info.subpixel_order = SubPixelHorizontalRGB;
325*4882a593Smuzhiyun connector->interlace_allowed = false;
326*4882a593Smuzhiyun connector->doublescan_allowed = false;
327*4882a593Smuzhiyun
328*4882a593Smuzhiyun drm_object_attach_property(&connector->base,
329*4882a593Smuzhiyun dev->mode_config.scaling_mode_property,
330*4882a593Smuzhiyun DRM_MODE_SCALE_FULLSCREEN);
331*4882a593Smuzhiyun drm_object_attach_property(&connector->base,
332*4882a593Smuzhiyun dev_priv->backlight_property,
333*4882a593Smuzhiyun BRIGHTNESS_MAX_LEVEL);
334*4882a593Smuzhiyun
335*4882a593Smuzhiyun mode_dev->panel_wants_dither = false;
336*4882a593Smuzhiyun if (dev_priv->has_gct)
337*4882a593Smuzhiyun mode_dev->panel_wants_dither = (dev_priv->gct_data.
338*4882a593Smuzhiyun Panel_Port_Control & MRST_PANEL_8TO6_DITHER_ENABLE);
339*4882a593Smuzhiyun if (dev_priv->lvds_dither)
340*4882a593Smuzhiyun mode_dev->panel_wants_dither = 1;
341*4882a593Smuzhiyun
342*4882a593Smuzhiyun /*
343*4882a593Smuzhiyun * LVDS discovery:
344*4882a593Smuzhiyun * 1) check for EDID on DDC
345*4882a593Smuzhiyun * 2) check for VBT data
346*4882a593Smuzhiyun * 3) check to see if LVDS is already on
347*4882a593Smuzhiyun * if none of the above, no panel
348*4882a593Smuzhiyun * 4) make sure lid is open
349*4882a593Smuzhiyun * if closed, act like it's not there for now
350*4882a593Smuzhiyun */
351*4882a593Smuzhiyun
352*4882a593Smuzhiyun edid = NULL;
353*4882a593Smuzhiyun mutex_lock(&dev->mode_config.mutex);
354*4882a593Smuzhiyun i2c_adap = i2c_get_adapter(dev_priv->ops->i2c_bus);
355*4882a593Smuzhiyun if (i2c_adap)
356*4882a593Smuzhiyun edid = drm_get_edid(connector, i2c_adap);
357*4882a593Smuzhiyun if (edid == NULL && dev_priv->lpc_gpio_base) {
358*4882a593Smuzhiyun oaktrail_lvds_i2c_init(encoder);
359*4882a593Smuzhiyun if (gma_encoder->ddc_bus != NULL) {
360*4882a593Smuzhiyun i2c_adap = &gma_encoder->ddc_bus->adapter;
361*4882a593Smuzhiyun edid = drm_get_edid(connector, i2c_adap);
362*4882a593Smuzhiyun }
363*4882a593Smuzhiyun }
364*4882a593Smuzhiyun /*
365*4882a593Smuzhiyun * Attempt to get the fixed panel mode from DDC. Assume that the
366*4882a593Smuzhiyun * preferred mode is the right one.
367*4882a593Smuzhiyun */
368*4882a593Smuzhiyun if (edid) {
369*4882a593Smuzhiyun drm_connector_update_edid_property(connector, edid);
370*4882a593Smuzhiyun drm_add_edid_modes(connector, edid);
371*4882a593Smuzhiyun kfree(edid);
372*4882a593Smuzhiyun
373*4882a593Smuzhiyun list_for_each_entry(scan, &connector->probed_modes, head) {
374*4882a593Smuzhiyun if (scan->type & DRM_MODE_TYPE_PREFERRED) {
375*4882a593Smuzhiyun mode_dev->panel_fixed_mode =
376*4882a593Smuzhiyun drm_mode_duplicate(dev, scan);
377*4882a593Smuzhiyun goto out; /* FIXME: check for quirks */
378*4882a593Smuzhiyun }
379*4882a593Smuzhiyun }
380*4882a593Smuzhiyun } else
381*4882a593Smuzhiyun dev_err(dev->dev, "No ddc adapter available!\n");
382*4882a593Smuzhiyun /*
383*4882a593Smuzhiyun * If we didn't get EDID, try geting panel timing
384*4882a593Smuzhiyun * from configuration data
385*4882a593Smuzhiyun */
386*4882a593Smuzhiyun oaktrail_lvds_get_configuration_mode(dev, mode_dev);
387*4882a593Smuzhiyun
388*4882a593Smuzhiyun if (mode_dev->panel_fixed_mode) {
389*4882a593Smuzhiyun mode_dev->panel_fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
390*4882a593Smuzhiyun goto out; /* FIXME: check for quirks */
391*4882a593Smuzhiyun }
392*4882a593Smuzhiyun
393*4882a593Smuzhiyun /* If we still don't have a mode after all that, give up. */
394*4882a593Smuzhiyun if (!mode_dev->panel_fixed_mode) {
395*4882a593Smuzhiyun dev_err(dev->dev, "Found no modes on the lvds, ignoring the LVDS\n");
396*4882a593Smuzhiyun goto failed_find;
397*4882a593Smuzhiyun }
398*4882a593Smuzhiyun
399*4882a593Smuzhiyun out:
400*4882a593Smuzhiyun mutex_unlock(&dev->mode_config.mutex);
401*4882a593Smuzhiyun
402*4882a593Smuzhiyun drm_connector_register(connector);
403*4882a593Smuzhiyun return;
404*4882a593Smuzhiyun
405*4882a593Smuzhiyun failed_find:
406*4882a593Smuzhiyun mutex_unlock(&dev->mode_config.mutex);
407*4882a593Smuzhiyun
408*4882a593Smuzhiyun dev_dbg(dev->dev, "No LVDS modes found, disabling.\n");
409*4882a593Smuzhiyun if (gma_encoder->ddc_bus) {
410*4882a593Smuzhiyun psb_intel_i2c_destroy(gma_encoder->ddc_bus);
411*4882a593Smuzhiyun gma_encoder->ddc_bus = NULL;
412*4882a593Smuzhiyun }
413*4882a593Smuzhiyun
414*4882a593Smuzhiyun /* failed_ddc: */
415*4882a593Smuzhiyun
416*4882a593Smuzhiyun drm_encoder_cleanup(encoder);
417*4882a593Smuzhiyun drm_connector_cleanup(connector);
418*4882a593Smuzhiyun kfree(gma_connector);
419*4882a593Smuzhiyun failed_connector:
420*4882a593Smuzhiyun kfree(gma_encoder);
421*4882a593Smuzhiyun }
422*4882a593Smuzhiyun
423