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Searched refs:PLLE_SS_CNTL_BYPASS_SS (Results 1 – 5 of 5) sorted by relevance

/OK3568_Linux_fs/u-boot/arch/arm/mach-tegra/tegra20/
H A Dclock.c626 #define PLLE_SS_CNTL_BYPASS_SS (1 << 10) macro
713 PLLE_SS_CNTL_BYPASS_SS; in tegra_plle_enable()
744 value &= ~PLLE_SS_CNTL_BYPASS_SS; in tegra_plle_enable()
/OK3568_Linux_fs/u-boot/arch/arm/mach-tegra/tegra30/
H A Dclock.c655 #define PLLE_SS_CNTL_BYPASS_SS (1 << 10) macro
759 PLLE_SS_CNTL_BYPASS_SS; in tegra_plle_enable()
790 value &= ~PLLE_SS_CNTL_BYPASS_SS; in tegra_plle_enable()
/OK3568_Linux_fs/u-boot/arch/arm/mach-tegra/tegra124/
H A Dclock.c940 #define PLLE_SS_CNTL_BYPASS_SS (1 << 10) macro
991 PLLE_SS_CNTL_BYPASS_SS; in tegra_plle_enable()
1028 value &= ~PLLE_SS_CNTL_BYPASS_SS; in tegra_plle_enable()
/OK3568_Linux_fs/u-boot/arch/arm/mach-tegra/tegra210/
H A Dclock.c1126 #define PLLE_SS_CNTL_BYPASS_SS (1 << 10) macro
1229 value &= ~PLLE_SS_CNTL_BYPASS_SS; in tegra_plle_enable()
/OK3568_Linux_fs/kernel/drivers/clk/tegra/
H A Dclk-pll.c70 #define PLLE_SS_CNTL_BYPASS_SS BIT(10) macro
75 #define PLLE_SS_DISABLE (PLLE_SS_CNTL_BYPASS_SS | PLLE_SS_CNTL_INTERP_RESET |\
1667 val &= ~(PLLE_SS_CNTL_SSC_BYP | PLLE_SS_CNTL_BYPASS_SS); in clk_plle_tegra114_enable()
2510 val &= ~(PLLE_SS_CNTL_SSC_BYP | PLLE_SS_CNTL_BYPASS_SS); in clk_plle_tegra210_enable()