Searched refs:INTR_STATUS (Results 1 – 10 of 10) sorted by relevance
| /OK3568_Linux_fs/u-boot/drivers/mtd/nand/raw/ |
| H A D | denali_spl.c | 46 intr_status = readl(denali_flash_reg + INTR_STATUS(flash_bank)); in wait_for_irq() 110 writel(0xffff, denali_flash_reg + INTR_STATUS(flash_bank)); in denali_send_pipeline_cmd()
|
| H A D | denali.h | 207 #define INTR_STATUS(bank) (0x410 + (bank) * 0x50) macro
|
| H A D | denali.c | 150 iowrite32(irq_status, denali->reg + INTR_STATUS(bank)); in denali_clear_irq() 167 irq_status = ioread32(denali->reg + INTR_STATUS(i)); in __denali_check_irq()
|
| /OK3568_Linux_fs/kernel/drivers/gpu/drm/msm/disp/dpu1/ |
| H A D | dpu_hwio.h | 15 #define INTR_STATUS 0x014 macro
|
| H A D | dpu_hw_interrupts.c | 199 MDP_SSPP_TOP0_OFF+INTR_STATUS
|
| /OK3568_Linux_fs/kernel/drivers/i3c/master/ |
| H A D | dw-i3c-master.c | 98 #define INTR_STATUS 0x3c macro 624 writel(INTR_ALL, master->regs + INTR_STATUS); in dw_i3c_master_bus_init() 1085 status = readl(master->regs + INTR_STATUS); in dw_i3c_master_irq_handler() 1088 writel(INTR_ALL, master->regs + INTR_STATUS); in dw_i3c_master_irq_handler() 1095 writel(INTR_TRANSFER_ERR_STAT, master->regs + INTR_STATUS); in dw_i3c_master_irq_handler() 1147 writel(INTR_ALL, master->regs + INTR_STATUS); in dw_i3c_probe()
|
| /OK3568_Linux_fs/kernel/drivers/staging/media/tegra-vde/ |
| H A D | vde.c | 33 #define INTR_STATUS 0x18 macro 147 err = readl_relaxed_poll_timeout(vde->bsev + INTR_STATUS, value, in tegra_vde_wait_bsev() 154 err = readl_relaxed_poll_timeout(vde->bsev + INTR_STATUS, value, in tegra_vde_wait_bsev() 164 err = readl_relaxed_poll_timeout(vde->bsev + INTR_STATUS, value, in tegra_vde_wait_bsev() 330 tegra_vde_writel(vde, 0x0003FC00, vde->bsev, INTR_STATUS); in tegra_vde_setup_hw_context()
|
| /OK3568_Linux_fs/kernel/drivers/mtd/nand/raw/ |
| H A D | denali.h | 208 #define INTR_STATUS(bank) (0x410 + (bank) * 0x50) macro
|
| H A D | cadence-nand-controller.c | 65 #define INTR_STATUS 0x0110 macro 726 writel_relaxed(irq_status->status, cdns_ctrl->reg + INTR_STATUS); in cadence_nand_clear_interrupt() 737 irq_status->status = readl_relaxed(cdns_ctrl->reg + INTR_STATUS); in cadence_nand_read_int_status() 1181 writel_relaxed(0xFFFFFFFF, cdns_ctrl->reg + INTR_STATUS); in cadence_nand_hw_init()
|
| H A D | denali.c | 111 iowrite32(irq_status, denali->reg + INTR_STATUS(bank)); in denali_clear_irq() 132 irq_status = ioread32(denali->reg + INTR_STATUS(i)); in denali_isr()
|