Searched refs:IMX7D_PLL_ENET_MAIN_100M_CLK (Results 1 – 11 of 11) sorted by relevance
186 <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>,192 <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
49 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;77 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
59 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
212 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;239 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
213 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;296 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
123 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
133 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
77 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
56 #define IMX7D_PLL_ENET_MAIN_100M_CLK 43 macro
52 #define IMX7D_PLL_ENET_MAIN_100M_CLK 43 macro
480 …hws[IMX7D_PLL_ENET_MAIN_100M_CLK] = imx_clk_hw_gate("pll_enet_100m_clk", "pll_enet_100m", base + 0… in imx7d_clocks_init()