xref: /OK3568_Linux_fs/kernel/arch/arm/boot/dts/imx7d-zii-rmu2.dts (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2*4882a593Smuzhiyun/*
3*4882a593Smuzhiyun * Device tree file for ZII's RMU2 board
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * RMU - Remote Modem Unit
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Copyright (C) 2019 Zodiac Inflight Innovations
8*4882a593Smuzhiyun */
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun/dts-v1/;
11*4882a593Smuzhiyun#include <dt-bindings/thermal/thermal.h>
12*4882a593Smuzhiyun#include "imx7d.dtsi"
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun/ {
15*4882a593Smuzhiyun	model = "ZII RMU2 Board";
16*4882a593Smuzhiyun	compatible = "zii,imx7d-rmu2", "fsl,imx7d";
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun	chosen {
19*4882a593Smuzhiyun		stdout-path = &uart2;
20*4882a593Smuzhiyun	};
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun	gpio-leds {
23*4882a593Smuzhiyun		compatible = "gpio-leds";
24*4882a593Smuzhiyun		pinctrl-0 = <&pinctrl_leds_debug>;
25*4882a593Smuzhiyun		pinctrl-names = "default";
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun		debug {
28*4882a593Smuzhiyun			label = "zii:green:debug1";
29*4882a593Smuzhiyun			gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>;
30*4882a593Smuzhiyun			linux,default-trigger = "heartbeat";
31*4882a593Smuzhiyun		};
32*4882a593Smuzhiyun	};
33*4882a593Smuzhiyun};
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun&cpu0 {
36*4882a593Smuzhiyun	cpu-supply = <&sw1a_reg>;
37*4882a593Smuzhiyun};
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun&ecspi1 {
40*4882a593Smuzhiyun	pinctrl-names = "default";
41*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_ecspi1>;
42*4882a593Smuzhiyun	cs-gpios = <&gpio4 19 GPIO_ACTIVE_LOW>;
43*4882a593Smuzhiyun	status = "okay";
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun	flash@0 {
46*4882a593Smuzhiyun		compatible = "jedec,spi-nor";
47*4882a593Smuzhiyun		spi-max-frequency = <20000000>;
48*4882a593Smuzhiyun		reg = <0>;
49*4882a593Smuzhiyun		#address-cells = <1>;
50*4882a593Smuzhiyun		#size-cells = <1>;
51*4882a593Smuzhiyun	};
52*4882a593Smuzhiyun};
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun&fec1 {
55*4882a593Smuzhiyun	pinctrl-names = "default";
56*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_enet1>;
57*4882a593Smuzhiyun	assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
58*4882a593Smuzhiyun			  <&clks IMX7D_ENET1_TIME_ROOT_CLK>;
59*4882a593Smuzhiyun	assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
60*4882a593Smuzhiyun	assigned-clock-rates = <0>, <100000000>;
61*4882a593Smuzhiyun	phy-mode = "rgmii-id";
62*4882a593Smuzhiyun	phy-handle = <&fec1_phy>;
63*4882a593Smuzhiyun	status = "okay";
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun	mdio {
66*4882a593Smuzhiyun		#address-cells = <1>;
67*4882a593Smuzhiyun		#size-cells = <0>;
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun		fec1_phy: ethernet-phy@0 {
70*4882a593Smuzhiyun			pinctrl-names = "default";
71*4882a593Smuzhiyun			pinctrl-0 = <&pinctrl_enet1_phy_reset>,
72*4882a593Smuzhiyun				    <&pinctrl_enet1_phy_interrupt>;
73*4882a593Smuzhiyun			reg = <0>;
74*4882a593Smuzhiyun			interrupt-parent = <&gpio1>;
75*4882a593Smuzhiyun			interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
76*4882a593Smuzhiyun			reset-gpios = <&gpio5 11 GPIO_ACTIVE_LOW>;
77*4882a593Smuzhiyun		};
78*4882a593Smuzhiyun	};
79*4882a593Smuzhiyun};
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun&i2c1 {
82*4882a593Smuzhiyun	clock-frequency = <100000>;
83*4882a593Smuzhiyun	pinctrl-names = "default";
84*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_i2c1>;
85*4882a593Smuzhiyun	status = "okay";
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun	pmic@8 {
88*4882a593Smuzhiyun		compatible = "fsl,pfuze3000";
89*4882a593Smuzhiyun		reg = <0x08>;
90*4882a593Smuzhiyun
91*4882a593Smuzhiyun		regulators {
92*4882a593Smuzhiyun			sw1a_reg: sw1a {
93*4882a593Smuzhiyun				regulator-min-microvolt = <700000>;
94*4882a593Smuzhiyun				regulator-max-microvolt = <3300000>;
95*4882a593Smuzhiyun				regulator-boot-on;
96*4882a593Smuzhiyun				regulator-always-on;
97*4882a593Smuzhiyun				regulator-ramp-delay = <6250>;
98*4882a593Smuzhiyun			};
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun			sw1c_reg: sw1b {
101*4882a593Smuzhiyun				regulator-min-microvolt = <700000>;
102*4882a593Smuzhiyun				regulator-max-microvolt = <1475000>;
103*4882a593Smuzhiyun				regulator-boot-on;
104*4882a593Smuzhiyun				regulator-always-on;
105*4882a593Smuzhiyun				regulator-ramp-delay = <6250>;
106*4882a593Smuzhiyun			};
107*4882a593Smuzhiyun
108*4882a593Smuzhiyun			sw2_reg: sw2 {
109*4882a593Smuzhiyun				regulator-min-microvolt = <1500000>;
110*4882a593Smuzhiyun				regulator-max-microvolt = <1850000>;
111*4882a593Smuzhiyun				regulator-boot-on;
112*4882a593Smuzhiyun				regulator-always-on;
113*4882a593Smuzhiyun			};
114*4882a593Smuzhiyun
115*4882a593Smuzhiyun			sw3a_reg: sw3 {
116*4882a593Smuzhiyun				regulator-min-microvolt = <900000>;
117*4882a593Smuzhiyun				regulator-max-microvolt = <1650000>;
118*4882a593Smuzhiyun				regulator-boot-on;
119*4882a593Smuzhiyun				regulator-always-on;
120*4882a593Smuzhiyun			};
121*4882a593Smuzhiyun
122*4882a593Smuzhiyun			swbst_reg: swbst {
123*4882a593Smuzhiyun				regulator-min-microvolt = <5000000>;
124*4882a593Smuzhiyun				regulator-max-microvolt = <5150000>;
125*4882a593Smuzhiyun			};
126*4882a593Smuzhiyun
127*4882a593Smuzhiyun			snvs_reg: vsnvs {
128*4882a593Smuzhiyun				regulator-min-microvolt = <1000000>;
129*4882a593Smuzhiyun				regulator-max-microvolt = <3000000>;
130*4882a593Smuzhiyun				regulator-boot-on;
131*4882a593Smuzhiyun				regulator-always-on;
132*4882a593Smuzhiyun			};
133*4882a593Smuzhiyun
134*4882a593Smuzhiyun			vref_reg: vrefddr {
135*4882a593Smuzhiyun				regulator-boot-on;
136*4882a593Smuzhiyun				regulator-always-on;
137*4882a593Smuzhiyun			};
138*4882a593Smuzhiyun
139*4882a593Smuzhiyun			vgen1_reg: vldo1 {
140*4882a593Smuzhiyun				regulator-min-microvolt = <1800000>;
141*4882a593Smuzhiyun				regulator-max-microvolt = <3300000>;
142*4882a593Smuzhiyun				regulator-always-on;
143*4882a593Smuzhiyun			};
144*4882a593Smuzhiyun
145*4882a593Smuzhiyun			vgen2_reg: vldo2 {
146*4882a593Smuzhiyun				regulator-min-microvolt = <800000>;
147*4882a593Smuzhiyun				regulator-max-microvolt = <1550000>;
148*4882a593Smuzhiyun				regulator-always-on;
149*4882a593Smuzhiyun			};
150*4882a593Smuzhiyun
151*4882a593Smuzhiyun			vgen3_reg: vccsd {
152*4882a593Smuzhiyun				regulator-min-microvolt = <2850000>;
153*4882a593Smuzhiyun				regulator-max-microvolt = <3300000>;
154*4882a593Smuzhiyun				regulator-always-on;
155*4882a593Smuzhiyun			};
156*4882a593Smuzhiyun
157*4882a593Smuzhiyun			vgen4_reg: v33 {
158*4882a593Smuzhiyun				regulator-min-microvolt = <2850000>;
159*4882a593Smuzhiyun				regulator-max-microvolt = <3300000>;
160*4882a593Smuzhiyun				regulator-always-on;
161*4882a593Smuzhiyun			};
162*4882a593Smuzhiyun
163*4882a593Smuzhiyun			vgen5_reg: vldo3 {
164*4882a593Smuzhiyun				regulator-min-microvolt = <1800000>;
165*4882a593Smuzhiyun				regulator-max-microvolt = <3300000>;
166*4882a593Smuzhiyun				regulator-always-on;
167*4882a593Smuzhiyun			};
168*4882a593Smuzhiyun
169*4882a593Smuzhiyun			vgen6_reg: vldo4 {
170*4882a593Smuzhiyun				regulator-min-microvolt = <1800000>;
171*4882a593Smuzhiyun				regulator-max-microvolt = <3300000>;
172*4882a593Smuzhiyun				regulator-always-on;
173*4882a593Smuzhiyun			};
174*4882a593Smuzhiyun		};
175*4882a593Smuzhiyun	};
176*4882a593Smuzhiyun
177*4882a593Smuzhiyun	eeprom@50 {
178*4882a593Smuzhiyun		compatible = "atmel,24c04";
179*4882a593Smuzhiyun		reg = <0x50>;
180*4882a593Smuzhiyun	};
181*4882a593Smuzhiyun
182*4882a593Smuzhiyun	eeprom@52 {
183*4882a593Smuzhiyun		compatible = "atmel,24c04";
184*4882a593Smuzhiyun		reg = <0x52>;
185*4882a593Smuzhiyun	};
186*4882a593Smuzhiyun};
187*4882a593Smuzhiyun
188*4882a593Smuzhiyun&snvs_rtc {
189*4882a593Smuzhiyun	status = "disabled";
190*4882a593Smuzhiyun};
191*4882a593Smuzhiyun
192*4882a593Smuzhiyun&uart2 {
193*4882a593Smuzhiyun	pinctrl-names = "default";
194*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_uart2>;
195*4882a593Smuzhiyun	assigned-clocks = <&clks IMX7D_UART2_ROOT_SRC>;
196*4882a593Smuzhiyun	assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
197*4882a593Smuzhiyun	status = "okay";
198*4882a593Smuzhiyun};
199*4882a593Smuzhiyun
200*4882a593Smuzhiyun&uart4 {
201*4882a593Smuzhiyun	pinctrl-names = "default";
202*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_uart4>;
203*4882a593Smuzhiyun	assigned-clocks = <&clks IMX7D_UART4_ROOT_SRC>;
204*4882a593Smuzhiyun	assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
205*4882a593Smuzhiyun	status = "okay";
206*4882a593Smuzhiyun
207*4882a593Smuzhiyun	rave-sp {
208*4882a593Smuzhiyun		compatible = "zii,rave-sp-rdu2";
209*4882a593Smuzhiyun		current-speed = <1000000>;
210*4882a593Smuzhiyun		#address-cells = <1>;
211*4882a593Smuzhiyun		#size-cells = <1>;
212*4882a593Smuzhiyun
213*4882a593Smuzhiyun		watchdog {
214*4882a593Smuzhiyun			compatible = "zii,rave-sp-watchdog";
215*4882a593Smuzhiyun		};
216*4882a593Smuzhiyun
217*4882a593Smuzhiyun		eeprom@a3 {
218*4882a593Smuzhiyun			compatible = "zii,rave-sp-eeprom";
219*4882a593Smuzhiyun			reg = <0xa3 0x4000>;
220*4882a593Smuzhiyun			#address-cells = <1>;
221*4882a593Smuzhiyun			#size-cells = <1>;
222*4882a593Smuzhiyun			zii,eeprom-name = "main-eeprom";
223*4882a593Smuzhiyun		};
224*4882a593Smuzhiyun	};
225*4882a593Smuzhiyun};
226*4882a593Smuzhiyun
227*4882a593Smuzhiyun&usbotg2 {
228*4882a593Smuzhiyun	dr_mode = "host";
229*4882a593Smuzhiyun	disable-over-current;
230*4882a593Smuzhiyun	status = "okay";
231*4882a593Smuzhiyun};
232*4882a593Smuzhiyun
233*4882a593Smuzhiyun&usdhc1 {
234*4882a593Smuzhiyun	pinctrl-names = "default";
235*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_usdhc1>;
236*4882a593Smuzhiyun	bus-width = <4>;
237*4882a593Smuzhiyun	no-1-8-v;
238*4882a593Smuzhiyun	no-sdio;
239*4882a593Smuzhiyun	keep-power-in-suspend;
240*4882a593Smuzhiyun	status = "okay";
241*4882a593Smuzhiyun};
242*4882a593Smuzhiyun
243*4882a593Smuzhiyun&usdhc3 {
244*4882a593Smuzhiyun	pinctrl-names = "default";
245*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_usdhc3>;
246*4882a593Smuzhiyun	bus-width = <8>;
247*4882a593Smuzhiyun	no-1-8-v;
248*4882a593Smuzhiyun	non-removable;
249*4882a593Smuzhiyun	no-sdio;
250*4882a593Smuzhiyun	no-sd;
251*4882a593Smuzhiyun	keep-power-in-suspend;
252*4882a593Smuzhiyun	status = "okay";
253*4882a593Smuzhiyun};
254*4882a593Smuzhiyun
255*4882a593Smuzhiyun&wdog1 {
256*4882a593Smuzhiyun	status = "disabled";
257*4882a593Smuzhiyun};
258*4882a593Smuzhiyun
259*4882a593Smuzhiyun&iomuxc {
260*4882a593Smuzhiyun	pinctrl_ecspi1: ecspi1grp {
261*4882a593Smuzhiyun		fsl,pins = <
262*4882a593Smuzhiyun			MX7D_PAD_ECSPI1_SCLK__ECSPI1_SCLK	0x2
263*4882a593Smuzhiyun			MX7D_PAD_ECSPI1_MOSI__ECSPI1_MOSI	0x2
264*4882a593Smuzhiyun			MX7D_PAD_ECSPI1_MISO__ECSPI1_MISO	0x2
265*4882a593Smuzhiyun			MX7D_PAD_ECSPI1_SS0__GPIO4_IO19         0x59
266*4882a593Smuzhiyun		>;
267*4882a593Smuzhiyun	};
268*4882a593Smuzhiyun
269*4882a593Smuzhiyun	pinctrl_enet1: enet1grp {
270*4882a593Smuzhiyun		fsl,pins = <
271*4882a593Smuzhiyun			MX7D_PAD_SD2_CD_B__ENET1_MDIO				0x3
272*4882a593Smuzhiyun			MX7D_PAD_SD2_WP__ENET1_MDC				0x3
273*4882a593Smuzhiyun			MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC		0x1
274*4882a593Smuzhiyun			MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0		0x1
275*4882a593Smuzhiyun			MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1		0x1
276*4882a593Smuzhiyun			MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2		0x1
277*4882a593Smuzhiyun			MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3		0x1
278*4882a593Smuzhiyun			MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL		0x1
279*4882a593Smuzhiyun			MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC		0x1
280*4882a593Smuzhiyun			MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0		0x1
281*4882a593Smuzhiyun			MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1		0x1
282*4882a593Smuzhiyun			MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2		0x1
283*4882a593Smuzhiyun			MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3		0x1
284*4882a593Smuzhiyun			MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL		0x1
285*4882a593Smuzhiyun		>;
286*4882a593Smuzhiyun	};
287*4882a593Smuzhiyun
288*4882a593Smuzhiyun	pinctrl_enet1_phy_reset: enet1phyresetgrp {
289*4882a593Smuzhiyun		fsl,pins = <
290*4882a593Smuzhiyun			MX7D_PAD_SD2_RESET_B__GPIO5_IO11	0x14
291*4882a593Smuzhiyun
292*4882a593Smuzhiyun		>;
293*4882a593Smuzhiyun	};
294*4882a593Smuzhiyun
295*4882a593Smuzhiyun	pinctrl_i2c1: i2c1grp {
296*4882a593Smuzhiyun		fsl,pins = <
297*4882a593Smuzhiyun			MX7D_PAD_I2C1_SDA__I2C1_SDA		0x4000007f
298*4882a593Smuzhiyun			MX7D_PAD_I2C1_SCL__I2C1_SCL		0x4000007f
299*4882a593Smuzhiyun		>;
300*4882a593Smuzhiyun	};
301*4882a593Smuzhiyun
302*4882a593Smuzhiyun	pinctrl_leds_debug: ledsgrp {
303*4882a593Smuzhiyun		fsl,pins = <
304*4882a593Smuzhiyun			MX7D_PAD_EPDC_DATA08__GPIO2_IO8		0x59
305*4882a593Smuzhiyun		>;
306*4882a593Smuzhiyun	};
307*4882a593Smuzhiyun
308*4882a593Smuzhiyun
309*4882a593Smuzhiyun	pinctrl_uart2: uart2grp {
310*4882a593Smuzhiyun		fsl,pins = <
311*4882a593Smuzhiyun			MX7D_PAD_UART2_RX_DATA__UART2_DCE_RX	0x79
312*4882a593Smuzhiyun			MX7D_PAD_UART2_TX_DATA__UART2_DCE_TX	0x79
313*4882a593Smuzhiyun		>;
314*4882a593Smuzhiyun	};
315*4882a593Smuzhiyun
316*4882a593Smuzhiyun	pinctrl_uart4: uart4grp {
317*4882a593Smuzhiyun		fsl,pins = <
318*4882a593Smuzhiyun			MX7D_PAD_SD2_DATA0__UART4_DCE_RX	0x79
319*4882a593Smuzhiyun			MX7D_PAD_SD2_DATA1__UART4_DCE_TX	0x79
320*4882a593Smuzhiyun		>;
321*4882a593Smuzhiyun	};
322*4882a593Smuzhiyun
323*4882a593Smuzhiyun	pinctrl_usdhc1: usdhc1grp {
324*4882a593Smuzhiyun		fsl,pins = <
325*4882a593Smuzhiyun			MX7D_PAD_SD1_CMD__SD1_CMD		0x59
326*4882a593Smuzhiyun			MX7D_PAD_SD1_CLK__SD1_CLK		0x19
327*4882a593Smuzhiyun			MX7D_PAD_SD1_DATA0__SD1_DATA0		0x59
328*4882a593Smuzhiyun			MX7D_PAD_SD1_DATA1__SD1_DATA1		0x59
329*4882a593Smuzhiyun			MX7D_PAD_SD1_DATA2__SD1_DATA2		0x59
330*4882a593Smuzhiyun			MX7D_PAD_SD1_DATA3__SD1_DATA3		0x59
331*4882a593Smuzhiyun		>;
332*4882a593Smuzhiyun	};
333*4882a593Smuzhiyun
334*4882a593Smuzhiyun	pinctrl_usdhc3: usdhc3grp {
335*4882a593Smuzhiyun		fsl,pins = <
336*4882a593Smuzhiyun			MX7D_PAD_SD3_CMD__SD3_CMD		0x59
337*4882a593Smuzhiyun			MX7D_PAD_SD3_CLK__SD3_CLK		0x19
338*4882a593Smuzhiyun			MX7D_PAD_SD3_DATA0__SD3_DATA0		0x59
339*4882a593Smuzhiyun			MX7D_PAD_SD3_DATA1__SD3_DATA1		0x59
340*4882a593Smuzhiyun			MX7D_PAD_SD3_DATA2__SD3_DATA2		0x59
341*4882a593Smuzhiyun			MX7D_PAD_SD3_DATA3__SD3_DATA3		0x59
342*4882a593Smuzhiyun			MX7D_PAD_SD3_DATA4__SD3_DATA4		0x59
343*4882a593Smuzhiyun			MX7D_PAD_SD3_DATA5__SD3_DATA5		0x59
344*4882a593Smuzhiyun			MX7D_PAD_SD3_DATA6__SD3_DATA6		0x59
345*4882a593Smuzhiyun			MX7D_PAD_SD3_DATA7__SD3_DATA7		0x59
346*4882a593Smuzhiyun			MX7D_PAD_SD3_RESET_B__SD3_RESET_B	0x59
347*4882a593Smuzhiyun		>;
348*4882a593Smuzhiyun	};
349*4882a593Smuzhiyun};
350*4882a593Smuzhiyun
351*4882a593Smuzhiyun&iomuxc_lpsr {
352*4882a593Smuzhiyun	pinctrl_enet1_phy_interrupt: enet1phyinterruptgrp {
353*4882a593Smuzhiyun		fsl,phy = <
354*4882a593Smuzhiyun			MX7D_PAD_LPSR_GPIO1_IO02__GPIO1_IO2	0x08
355*4882a593Smuzhiyun		>;
356*4882a593Smuzhiyun	};
357*4882a593Smuzhiyun};
358