Searched refs:EMI1_SLOT5 (Results 1 – 6 of 6) sorted by relevance
73 #define EMI1_SLOT5 4 macro559 lane_to_slot_fsm2[1] = EMI1_SLOT5; in initialize_dpmac_to_slot()560 lane_to_slot_fsm2[2] = EMI1_SLOT5; in initialize_dpmac_to_slot()561 lane_to_slot_fsm2[3] = EMI1_SLOT5; in initialize_dpmac_to_slot()565 lane_to_slot_fsm2[5] = EMI1_SLOT5; in initialize_dpmac_to_slot()566 lane_to_slot_fsm2[6] = EMI1_SLOT5; in initialize_dpmac_to_slot()567 lane_to_slot_fsm2[7] = EMI1_SLOT5; in initialize_dpmac_to_slot()582 lane_to_slot_fsm2[6] = EMI1_SLOT5; in initialize_dpmac_to_slot()583 lane_to_slot_fsm2[7] = EMI1_SLOT5; in initialize_dpmac_to_slot()715 dpmac_info[dpmac_id].board_mux = EMI1_SLOT5; in ls2080a_handle_phy_interface_sgmii()[all …]
34 #define EMI1_SLOT5 0xc0000000 /* bank3 ABCD */ macro276 case EMI1_SLOT5: in fdt_fixup_board_enet()323 p4080ds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT5); in board_eth_init()361 mdio_mux[i] = EMI1_SLOT5; in board_eth_init()377 bus = mii_dev_for_muxval(EMI1_SLOT5); in board_eth_init()428 mdio_mux[i] = EMI1_SLOT5; in board_eth_init()
59 #define EMI1_SLOT5 5 macro333 case EMI1_SLOT5: in fdt_fixup_board_enet()401 mdio_mux[i] = EMI1_SLOT5; in t1040_handle_phy_interface_sgmii()472 t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT5); in board_eth_init()
39 #define EMI1_SLOT5 5 macro44 #define EMI1_SLOT5 5 macro329 } else if (mdio_mux[port] == EMI1_SLOT5) { in board_ft_fman_fixup_port()558 t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT5); in board_eth_init()736 mdio_mux[i] = EMI1_SLOT5; in board_eth_init()
37 #define EMI1_SLOT5 6 macro294 t1024qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT5); in board_eth_init()405 mdio_mux[i] = EMI1_SLOT5; in board_eth_init()
38 #define EMI1_SLOT5 5 macro528 t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT5); in board_eth_init()