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/OK3568_Linux_fs/kernel/drivers/gpu/drm/nouveau/nvkm/subdev/fb/
H A Dgddr3.c73 int CL, WR, CWL, DLL = 0, ODT = 0, RON, hi; in nvkm_gddr3_calc() local
80 DLL = !ram->next->bios.ramcfg_DLLoff; in nvkm_gddr3_calc()
89 DLL = !(ram->mr[1] & 0x1); in nvkm_gddr3_calc()
117 ram->mr[1] |= !DLL << 6; in nvkm_gddr3_calc()
H A Dsddr2.c63 int CL, WR, DLL = 0, ODT = 0; in nvkm_sddr2_calc() local
69 DLL = !ram->next->bios.ramcfg_DLLoff; in nvkm_sddr2_calc()
98 ram->mr[1] |= !DLL; in nvkm_sddr2_calc()
H A Dsddr3.c72 int CWL, CL, WR, DLL = 0, ODT = 0; in nvkm_sddr3_calc() local
74 DLL = !ram->next->bios.ramcfg_DLLoff; in nvkm_sddr3_calc()
115 ram->mr[1] |= !DLL; in nvkm_sddr3_calc()
/OK3568_Linux_fs/buildroot/dl/sox/git/
H A DREADME.win328 restriction is that the included ZLIB1..DLL and LIBGOMP-1.DLL must be
89 with the DLL's that perform decoding and encoding of MP3 data because
94 MP3 support can be enabled by placing Lame encoding DLL and/or
95 MAD decoding DLL into the same directory as SOX.EXE. These
102 Instructions are included here for using MSYS to create the DLL's.
118 building DLL under mingw. This can be resolved by adding LDFLAGS
132 does not ship with the DLL's that perform decoding and encoding of AMR
135 AMR-NB/AMR-WB support can be enabled by placing required DLL's
143 Instructions are included here for using MSYS to create the DLL's.
/OK3568_Linux_fs/kernel/arch/arm/mach-omap2/
H A Dsleep24xx.S60 mov r5, #0x2000 @ set delay (DPLL relock + DLL relock)
76 strne r0, [r1] @ rewrite DLLA to force DLL reload
78 strne r0, [r1] @ rewrite DLLB to force DLL reload
H A Dsram243x.S52 orr r10, r10, #0x8 @ make sure DLL on (es2 bit pos)
86 mov r4, #0x800 @ delay DLL relock, min 0x400 L3 clocks
172 cmp r2, #0x1 @ (SDR or DDR) do we need to adjust DLL
173 bne freq_out @ leave if SDR, no DLL function
180 mov r1, #0x2000 @ wait DLL relock, min 0x400 L3 clocks
291 orr r10, r10, #0x8 @ make sure DLL on (es2 bit pos)
H A Dsram242x.S52 orr r10, r10, #0x8 @ make sure DLL on (es2 bit pos)
86 mov r4, #0x800 @ delay DLL relock, min 0x400 L3 clocks
172 cmp r2, #0x1 @ (SDR or DDR) do we need to adjust DLL
173 bne freq_out @ leave if SDR, no DLL function
180 mov r1, #0x2000 @ wait DLL relock, min 0x400 L3 clocks
291 orr r10, r10, #0x8 @ make sure DLL on (es2 bit pos)
/OK3568_Linux_fs/yocto/meta-openembedded/meta-networking/recipes-connectivity/bearssl/bearssl/
H A D0001-conf-Unix.mk-remove-fixed-command-definitions.patch33 # DLL building tool.
49 # (e.g. 'make dll' to force build the DLL).
52 #DLL = no
/OK3568_Linux_fs/kernel/arch/x86/boot/
H A Dearly_serial_console.c21 #define DLL 0 /* Divisor Latch Low */ macro
39 outb(divisor & 0xff, port + DLL); in early_serial_init()
109 dll = inb(port + DLL); in probe_baud()
/OK3568_Linux_fs/rkbin/doc/release/
H A DRK3566_CN.md88 | 2 | 重要 | DDR4 528M稳定性问题 | 个别颗粒528M下无法开启DLL，需要做关闭DLL处理. | - …
H A DRK3568_CN.md312 | 3 | 重要 | DDR4 528M稳定性问题 | 个别颗粒528M下无法开启DLL，需要做关闭DLL处理. | -…
H A DRK3566_EN.md88 …4 528M stability problem | some DRAM DLL can't lock at 528M，DLL should b…
H A DRK3308_CN.md25 | 1 | 普通 | 提高部分颗粒在 RK3308B/H 上 393MHz 的稳定性 | RK3308B/H 小于 451MHz 时 Read DQS DLL delay 的值配置不…
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/devfreq/
H A Drk3399_dmc.txt62 - rockchip,dram_dll_dis_freq : Defines the DDR3 DLL bypass frequency in MHz.
64 DDR3 DLL will be bypassed. Note: if DLL was bypassed,
69 DRAM_DLL_DISB_FREQ, PHY DLL will be bypassed.
70 Note: PHY DLL and PHY ODT are independent.
/OK3568_Linux_fs/kernel/tools/testing/kunit/
H A D.gitignore2 # Byte-compiled / optimized / DLL files
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/mmc/
H A Dsdhci-sprd.txt26 PHY DLL delays are used to delay the data valid window, and align the window
27 to sampling clock. PHY DLL delays can be configured by following properties,
H A Dsdhci-st.txt27 to configure DLL inside the flashSS, if so reg-names must also be
32 for eMMC on stih407 family silicon to configure DLL inside FlashSS.
/OK3568_Linux_fs/kernel/arch/x86/kernel/
H A Dearly_printk.c94 #define DLL 0 /* Divisor Latch Low */ macro
141 serial_out(early_serial_base, DLL, divisor & 0xff); in early_serial_hw_init()
/OK3568_Linux_fs/yocto/poky/meta/recipes-extended/unzip/unzip/
H A DCVE-2015-7697.patch28 #if (defined(DLL) && !defined(NO_SLIDE_REDIR))
/OK3568_Linux_fs/u-boot/board/Seagate/nas220/
H A Dkwbimage.cfg92 # bit8: 0, DLL reset=0 normal
99 # bit0: 0, DDR DLL enabled
/OK3568_Linux_fs/u-boot/board/Marvell/guruplug/
H A Dkwbimage.cfg89 # bit8: 0, DLL reset=0 normal
95 # bit0: 0, DDR DLL enabled
/OK3568_Linux_fs/u-boot/board/Seagate/dockstar/
H A Dkwbimage.cfg92 # bit8: 0, DLL reset=0 normal
98 # bit0: 0, DDR DLL enabled
/OK3568_Linux_fs/u-boot/board/Synology/ds109/
H A Dkwbimage.cfg93 # bit8: 0, DLL reset=0 normal
99 # bit0: 0, DDR DLL enabled
/OK3568_Linux_fs/u-boot/board/Marvell/dreamplug/
H A Dkwbimage.cfg90 # bit8: 0, DLL reset=0 normal
96 # bit0: 0, DDR DLL enabled
/OK3568_Linux_fs/u-boot/board/Seagate/goflexhome/
H A Dkwbimage.cfg95 # bit8: 0, DLL reset=0 normal
101 # bit0: 0, DDR DLL enabled

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