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Searched refs:CRTC (Results 1 – 25 of 65) sorted by relevance

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/OK3568_Linux_fs/kernel/drivers/gpu/drm/nouveau/dispnv04/
H A Dcrtc.c60 crtcstate->CRTC[index]); in crtc_wr_cio_state()
69 regp->CRTC[NV_CIO_CRE_CSB] = nv_crtc->saturation = level; in nv_crtc_set_digital_vibrance()
71 regp->CRTC[NV_CIO_CRE_CSB] = 0x80; in nv_crtc_set_digital_vibrance()
72 regp->CRTC[NV_CIO_CRE_5B] = nv_crtc->saturation << 2; in nv_crtc_set_digital_vibrance()
345 regp->CRTC[NV_CIO_CR_HDT_INDEX] = horizTotal; in nv_crtc_mode_set_vga()
346 regp->CRTC[NV_CIO_CR_HDE_INDEX] = horizDisplay; in nv_crtc_mode_set_vga()
347 regp->CRTC[NV_CIO_CR_HBS_INDEX] = horizBlankStart; in nv_crtc_mode_set_vga()
348 regp->CRTC[NV_CIO_CR_HBE_INDEX] = (1 << 7) | in nv_crtc_mode_set_vga()
350 regp->CRTC[NV_CIO_CR_HRS_INDEX] = horizStart; in nv_crtc_mode_set_vga()
351 regp->CRTC[NV_CIO_CR_HRE_INDEX] = XLATE(horizBlankEnd, 5, NV_CIO_CR_HRE_HBE_5) | in nv_crtc_mode_set_vga()
[all …]
H A Dcursor.c34 crtcstate->CRTC[index]); in crtc_wr_cio_state()
45 regp->CRTC[NV_CIO_CRE_HCUR_ADDR0_INDEX] = in nv04_cursor_set_offset()
48 regp->CRTC[NV_CIO_CRE_HCUR_ADDR1_INDEX] = in nv04_cursor_set_offset()
51 regp->CRTC[NV_CIO_CRE_HCUR_ADDR1_INDEX] |= in nv04_cursor_set_offset()
53 regp->CRTC[NV_CIO_CRE_HCUR_ADDR2_INDEX] = offset >> 24; in nv04_cursor_set_offset()
H A Dtvnv04.c112 state->CRTC[NV_CIO_CRE_49] |= 0x10; in nv04_tv_bind()
114 state->CRTC[NV_CIO_CRE_49] &= ~0x10; in nv04_tv_bind()
117 state->CRTC[NV_CIO_CRE_LCD__INDEX]); in nv04_tv_bind()
119 state->CRTC[NV_CIO_CRE_49]); in nv04_tv_bind()
/OK3568_Linux_fs/external/xserver/hw/xfree86/vgahw/
H A DvgaHW.c861 hwp->writeCrtc(hwp, 17, restore->CRTC[17] & ~0x80); in vgaHWRestoreMode()
864 hwp->writeCrtc(hwp, i, restore->CRTC[i]); in vgaHWRestoreMode()
1028 save->CRTC[i] = hwp->readCrtc(hwp, i); in vgaHWSaveMode()
1029 DebugF("CRTC[0x%02x] = 0x%02x\n", i, save->CRTC[i]); in vgaHWSaveMode()
1240 regp->CRTC[0] = (mode->CrtcHTotal >> 3) - 5; in vgaHWInit()
1241 regp->CRTC[1] = (mode->CrtcHDisplay >> 3) - 1; in vgaHWInit()
1242 regp->CRTC[2] = (mode->CrtcHBlankStart >> 3) - 1; in vgaHWInit()
1243 regp->CRTC[3] = (((mode->CrtcHBlankEnd >> 3) - 1) & 0x1F) | 0x80; in vgaHWInit()
1246 regp->CRTC[3] |= i; in vgaHWInit()
1247 regp->CRTC[4] = (mode->CrtcHSyncStart >> 3); in vgaHWInit()
[all …]
/OK3568_Linux_fs/kernel/drivers/video/fbdev/matrox/
H A Dmatroxfb_misc.c304 hw->CRTC[0] = ht-4; in matroxfb_vgaHWinit()
305 hw->CRTC[1] = hd; in matroxfb_vgaHWinit()
306 hw->CRTC[2] = hd; in matroxfb_vgaHWinit()
307 hw->CRTC[3] = (hbe & 0x1F) | 0x80; in matroxfb_vgaHWinit()
308 hw->CRTC[4] = hs; in matroxfb_vgaHWinit()
309 hw->CRTC[5] = ((hbe & 0x20) << 2) | (he & 0x1F); in matroxfb_vgaHWinit()
310 hw->CRTC[6] = vt & 0xFF; in matroxfb_vgaHWinit()
311 hw->CRTC[7] = ((vt & 0x100) >> 8) | in matroxfb_vgaHWinit()
319 hw->CRTC[8] = 0x00; in matroxfb_vgaHWinit()
320 hw->CRTC[9] = ((vd & 0x200) >> 4) | in matroxfb_vgaHWinit()
[all …]
/OK3568_Linux_fs/yocto/meta-rockchip/recipes-graphics/wayland/weston_11.0.1/
H A D0006-backend-drm-Bind-Nth-primary-plane-to-Nth-CRTC.patch4 Subject: [PATCH 06/93] backend-drm: Bind Nth primary plane to Nth CRTC
6 The vop2 allows primary planes to bind with random CRTC, but we need to
21 int pipe; /* index of CRTC in resource array / bitmasks */
25 /* Holds the properties for the CRTC */
36 + /* The plane is not the primary plane for this CRTC. */
41 /* Check whether the plane can be used with this CRTC; possible_crtcs
42 * is a bitmask of CRTC indices (pipe), rather than CRTC object ID. */
H A D0040-HACK-backend-drm-Workaround-atomic-flip-for-BSP-4.4-.patch21 drm_debug(b, "[atomic][CRTC:%u] flip processing started\n", crtc_id);
/OK3568_Linux_fs/buildroot/package/weston/
H A D0006-backend-drm-Bind-Nth-primary-plane-to-Nth-CRTC.patch4 Subject: [PATCH 06/93] backend-drm: Bind Nth primary plane to Nth CRTC
6 The vop2 allows primary planes to bind with random CRTC, but we need to
21 int pipe; /* index of CRTC in resource array / bitmasks */
25 /* Holds the properties for the CRTC */
36 + /* The plane is not the primary plane for this CRTC. */
41 /* Check whether the plane can be used with this CRTC; possible_crtcs
42 * is a bitmask of CRTC indices (pipe), rather than CRTC object ID. */
H A D0040-HACK-backend-drm-Workaround-atomic-flip-for-BSP-4.4-.patch21 drm_debug(b, "[atomic][CRTC:%u] flip processing started\n", crtc_id);
/OK3568_Linux_fs/external/xserver/hw/xfree86/doc/
H A DREADME.modes9 underlying hardware CRTC and output concepts to the xf86 DDX layer so that
30 the 'CRTC' (xf86CrtcRec) and the 'Output' (xf86OutputRec). A CRTC refers to
57 other outputs which can be simutaneously connected to a CRTC.
59 2.1.2 CRTC overview
92 This function allocates and initializes structures needed to track CRTC and
106 Create one CRTC object. See the discussion below for a description of the
109 each CRTC present in the hardware.
235 Applies a mode to a CRTC. All of the outputs which are currently using the
236 specified CRTC are included in the mode setting process. 'x' and 'y' are the
255 operations. The current 'desired' mode for the CRTC associated with the
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/OK3568_Linux_fs/kernel/drivers/video/fbdev/
H A Dneofb.c283 par->CRTC[0] = htotal - 5; in vgaHWInit()
284 par->CRTC[1] = (var->xres >> 3) - 1; in vgaHWInit()
285 par->CRTC[2] = (var->xres >> 3) - 1; in vgaHWInit()
286 par->CRTC[3] = ((htotal - 1) & 0x1F) | 0x80; in vgaHWInit()
287 par->CRTC[4] = ((var->xres + var->right_margin) >> 3); in vgaHWInit()
288 par->CRTC[5] = (((htotal - 1) & 0x20) << 2) in vgaHWInit()
290 par->CRTC[6] = (vtotal - 2) & 0xFF; in vgaHWInit()
291 par->CRTC[7] = (((vtotal - 2) & 0x100) >> 8) in vgaHWInit()
298 par->CRTC[8] = 0x00; in vgaHWInit()
299 par->CRTC[9] = (((var->yres - 1) & 0x200) >> 4) | 0x40; in vgaHWInit()
[all …]
/OK3568_Linux_fs/kernel/drivers/video/fbdev/savage/
H A Dsavagefb_driver.c127 VGAwCR(17, reg->CRTC[17] & ~0x80, par); in vgaHWRestore()
130 VGAwCR(i, reg->CRTC[i], par); in vgaHWRestore()
168 reg->CRTC[0x00] = (timings->HTotal >> 3) - 5; in vgaHWInit()
169 reg->CRTC[0x01] = (timings->HDisplay >> 3) - 1; in vgaHWInit()
170 reg->CRTC[0x02] = (timings->HSyncStart >> 3) - 1; in vgaHWInit()
171 reg->CRTC[0x03] = (((timings->HSyncEnd >> 3) - 1) & 0x1f) | 0x80; in vgaHWInit()
172 reg->CRTC[0x04] = (timings->HSyncStart >> 3); in vgaHWInit()
173 reg->CRTC[0x05] = ((((timings->HSyncEnd >> 3) - 1) & 0x20) << 2) | in vgaHWInit()
175 reg->CRTC[0x06] = (timings->VTotal - 2) & 0xFF; in vgaHWInit()
176 reg->CRTC[0x07] = (((timings->VTotal - 2) & 0x100) >> 8) | in vgaHWInit()
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/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/display/dc/dce/
H A Ddce_hwseq.h104 SRII(CRTC_H_BLANK_START_END, CRTC, 0),\
105 SRII(CRTC_H_BLANK_START_END, CRTC, 1),\
111 HWSEQ_PIXEL_RATE_REG_LIST(CRTC)
116 HWSEQ_PIXEL_RATE_REG_LIST(CRTC)
122 HWSEQ_PIXEL_RATE_REG_LIST(CRTC)
127 HWSEQ_PIXEL_RATE_REG_LIST(CRTC)
139 SRII(CRTC_H_BLANK_START_END, CRTC, 2), \
149 HWSEQ_PIXEL_RATE_REG_LIST(CRTC), \
150 HWSEQ_PHYPLL_REG_LIST(CRTC), \
162 HWSEQ_PIXEL_RATE_REG_LIST(CRTC), \
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H A Ddce_transform.h99 SRI(DCFE_MEM_LIGHT_SLEEP_CNTL, CRTC, id)
103 SRI(DCFE_MEM_PWR_CTRL, CRTC, id), \
104 SRI(DCFE_MEM_PWR_STATUS, CRTC, id)
164 SRI(DCFE_MEM_LIGHT_SLEEP_CNTL, CRTC, id), \
170 SRI(DCFE_MEM_LIGHT_SLEEP_CNTL, CRTC, id)
/OK3568_Linux_fs/kernel/Documentation/gpu/
H A Dkms-properties.csv61 armada,CRTC,"""CSC_YUV""",ENUM,"{ ""Auto"" , ""CCIR601"", ""CCIR709"" }",CRTC,TBD
62 ,,"""CSC_RGB""",ENUM,"{ ""Auto"", ""Computer system"", ""Studio"" }",CRTC,TBD
72 exynos,CRTC,“mode”,ENUM,"{ ""normal"", ""blank"" }",CRTC,TBD
90 omap,Generic,“zorder”,RANGE,"Min=0, Max=3","CRTC, Plane",TBD
H A Ddrm-kms.rst61 details. One or more (or even no) planes feed their pixel data into a CRTC
62 (represented by :c:type:`struct drm_crtc <drm_crtc>`, see `CRTC Abstraction`_)
70 to figure out which connections between a CRTC and a connector are possible, and
75 A CRTC can be connected to multiple encoders, and for an active CRTC there must
140 the CRTC and any encoders. Often for drivers with bridges there's no code left
307 CRTC Abstraction
313 CRTC Functions Reference
463 Standard CRTC Properties
467 :doc: standard CRTC properties
H A Dvc4.rst15 Pixel Valve (DRM CRTC)
19 :doc: VC4 CRTC module
/OK3568_Linux_fs/buildroot/package/vkmark/
H A D0001-kms-Use-Nth-primary-plane-for-Nth-CRTC.patch4 Subject: [PATCH 1/3] kms: Use Nth primary plane for Nth CRTC
30 + /* Nth primary plane for Nth CRTC */
/OK3568_Linux_fs/yocto/meta-rockchip/recipes-graphics/wayland/weston_10.0.2/
H A D0005-backend-drm-Bind-Nth-primary-plane-to-Nth-CRTC.patch4 Subject: [PATCH 05/79] backend-drm: Bind Nth primary plane to Nth CRTC
6 The vop2 allows primary planes to bind with random CRTC, but we need to
H A D0037-HACK-backend-drm-Workaround-atomic-flip-for-BSP-4.4-.patch21 drm_debug(b, "[atomic][CRTC:%u] flip processing started\n", crtc_id);
/OK3568_Linux_fs/buildroot/package/efl/
H A D0006-ecore_drm2-Fallback-to-first-possible-CRTC-of-encode.patch4 Subject: [PATCH 06/10] ecore_drm2: Fallback to first possible CRTC of encoder
6 TODO: Avoid using assigned CRTC.
/OK3568_Linux_fs/external/drm-cursor/debian/
H A Dchangelog40 * Update CRTC status when setting cursor
51 * Cache CRTC size
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/display/dc/irq/dce120/
H A Dirq_service_dce120.c147 IRQ_REG_ENTRY(CRTC, reg_num,\
155 IRQ_REG_ENTRY(CRTC, reg_num,\
/OK3568_Linux_fs/kernel/drivers/usb/misc/sisusbvga/
H A Dsisusb_struct.h74 unsigned char CRTC[0x19]; member
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/display/armada/
H A Dmarvell,dove-lcd.txt1 Device Tree bindings for Armada DRM CRTC driver

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