1*4882a593SmuzhiyunDevice Tree bindings for Armada DRM CRTC driver 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired properties: 4*4882a593Smuzhiyun - compatible: value should be "marvell,dove-lcd". 5*4882a593Smuzhiyun - reg: base address and size of the LCD controller 6*4882a593Smuzhiyun - interrupts: single interrupt number for the LCD controller 7*4882a593Smuzhiyun - port: video output port with endpoints, as described by graph.txt 8*4882a593Smuzhiyun 9*4882a593SmuzhiyunOptional properties: 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun - clocks: as described by clock-bindings.txt 12*4882a593Smuzhiyun - clock-names: as described by clock-bindings.txt 13*4882a593Smuzhiyun "axiclk" - axi bus clock for pixel clock 14*4882a593Smuzhiyun "plldivider" - pll divider clock for pixel clock 15*4882a593Smuzhiyun "ext_ref_clk0" - external clock 0 for pixel clock 16*4882a593Smuzhiyun "ext_ref_clk1" - external clock 1 for pixel clock 17*4882a593Smuzhiyun 18*4882a593SmuzhiyunNote: all clocks are optional but at least one must be specified. 19*4882a593SmuzhiyunFurther clocks may be added in the future according to requirements of 20*4882a593Smuzhiyundifferent SoCs. 21*4882a593Smuzhiyun 22*4882a593SmuzhiyunExample: 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun lcd0: lcd-controller@820000 { 25*4882a593Smuzhiyun compatible = "marvell,dove-lcd"; 26*4882a593Smuzhiyun reg = <0x820000 0x1000>; 27*4882a593Smuzhiyun interrupts = <47>; 28*4882a593Smuzhiyun clocks = <&si5351 0>; 29*4882a593Smuzhiyun clock-names = "ext_ref_clk_1"; 30*4882a593Smuzhiyun }; 31