xref: /OK3568_Linux_fs/kernel/drivers/gpu/drm/nouveau/dispnv04/tvnv04.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun  * Copyright (C) 2009 Francisco Jerez.
3*4882a593Smuzhiyun  * All Rights Reserved.
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Permission is hereby granted, free of charge, to any person obtaining
6*4882a593Smuzhiyun  * a copy of this software and associated documentation files (the
7*4882a593Smuzhiyun  * "Software"), to deal in the Software without restriction, including
8*4882a593Smuzhiyun  * without limitation the rights to use, copy, modify, merge, publish,
9*4882a593Smuzhiyun  * distribute, sublicense, and/or sell copies of the Software, and to
10*4882a593Smuzhiyun  * permit persons to whom the Software is furnished to do so, subject to
11*4882a593Smuzhiyun  * the following conditions:
12*4882a593Smuzhiyun  *
13*4882a593Smuzhiyun  * The above copyright notice and this permission notice (including the
14*4882a593Smuzhiyun  * next paragraph) shall be included in all copies or substantial
15*4882a593Smuzhiyun  * portions of the Software.
16*4882a593Smuzhiyun  *
17*4882a593Smuzhiyun  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
18*4882a593Smuzhiyun  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19*4882a593Smuzhiyun  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20*4882a593Smuzhiyun  * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
21*4882a593Smuzhiyun  * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
22*4882a593Smuzhiyun  * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
23*4882a593Smuzhiyun  * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
24*4882a593Smuzhiyun  *
25*4882a593Smuzhiyun  */
26*4882a593Smuzhiyun 
27*4882a593Smuzhiyun #include "nouveau_drv.h"
28*4882a593Smuzhiyun #include "nouveau_reg.h"
29*4882a593Smuzhiyun #include "nouveau_encoder.h"
30*4882a593Smuzhiyun #include "nouveau_connector.h"
31*4882a593Smuzhiyun #include "nouveau_crtc.h"
32*4882a593Smuzhiyun #include "hw.h"
33*4882a593Smuzhiyun #include <drm/drm_crtc_helper.h>
34*4882a593Smuzhiyun 
35*4882a593Smuzhiyun #include <drm/i2c/ch7006.h>
36*4882a593Smuzhiyun 
37*4882a593Smuzhiyun static struct nvkm_i2c_bus_probe nv04_tv_encoder_info[] = {
38*4882a593Smuzhiyun 	{
39*4882a593Smuzhiyun 		{
40*4882a593Smuzhiyun 			I2C_BOARD_INFO("ch7006", 0x75),
41*4882a593Smuzhiyun 			.platform_data = &(struct ch7006_encoder_params) {
42*4882a593Smuzhiyun 				CH7006_FORMAT_RGB24m12I, CH7006_CLOCK_MASTER,
43*4882a593Smuzhiyun 				0, 0, 0,
44*4882a593Smuzhiyun 				CH7006_SYNC_SLAVE, CH7006_SYNC_SEPARATED,
45*4882a593Smuzhiyun 				CH7006_POUT_3_3V, CH7006_ACTIVE_HSYNC
46*4882a593Smuzhiyun 			}
47*4882a593Smuzhiyun 		},
48*4882a593Smuzhiyun 		0
49*4882a593Smuzhiyun 	},
50*4882a593Smuzhiyun 	{ }
51*4882a593Smuzhiyun };
52*4882a593Smuzhiyun 
nv04_tv_identify(struct drm_device * dev,int i2c_index)53*4882a593Smuzhiyun int nv04_tv_identify(struct drm_device *dev, int i2c_index)
54*4882a593Smuzhiyun {
55*4882a593Smuzhiyun 	struct nouveau_drm *drm = nouveau_drm(dev);
56*4882a593Smuzhiyun 	struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device);
57*4882a593Smuzhiyun 	struct nvkm_i2c_bus *bus = nvkm_i2c_bus_find(i2c, i2c_index);
58*4882a593Smuzhiyun 	if (bus) {
59*4882a593Smuzhiyun 		return nvkm_i2c_bus_probe(bus, "TV encoder",
60*4882a593Smuzhiyun 					  nv04_tv_encoder_info,
61*4882a593Smuzhiyun 					  NULL, NULL);
62*4882a593Smuzhiyun 	}
63*4882a593Smuzhiyun 	return -ENODEV;
64*4882a593Smuzhiyun }
65*4882a593Smuzhiyun 
66*4882a593Smuzhiyun 
67*4882a593Smuzhiyun #define PLLSEL_TV_CRTC1_MASK				\
68*4882a593Smuzhiyun 	(NV_PRAMDAC_PLL_COEFF_SELECT_TV_VSCLK1		\
69*4882a593Smuzhiyun 	 | NV_PRAMDAC_PLL_COEFF_SELECT_TV_PCLK1)
70*4882a593Smuzhiyun #define PLLSEL_TV_CRTC2_MASK				\
71*4882a593Smuzhiyun 	(NV_PRAMDAC_PLL_COEFF_SELECT_TV_VSCLK2		\
72*4882a593Smuzhiyun 	 | NV_PRAMDAC_PLL_COEFF_SELECT_TV_PCLK2)
73*4882a593Smuzhiyun 
nv04_tv_dpms(struct drm_encoder * encoder,int mode)74*4882a593Smuzhiyun static void nv04_tv_dpms(struct drm_encoder *encoder, int mode)
75*4882a593Smuzhiyun {
76*4882a593Smuzhiyun 	struct drm_device *dev = encoder->dev;
77*4882a593Smuzhiyun 	struct nouveau_drm *drm = nouveau_drm(dev);
78*4882a593Smuzhiyun 	struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
79*4882a593Smuzhiyun 	struct nv04_mode_state *state = &nv04_display(dev)->mode_reg;
80*4882a593Smuzhiyun 	uint8_t crtc1A;
81*4882a593Smuzhiyun 
82*4882a593Smuzhiyun 	NV_DEBUG(drm, "Setting dpms mode %d on TV encoder (output %d)\n",
83*4882a593Smuzhiyun 		 mode, nv_encoder->dcb->index);
84*4882a593Smuzhiyun 
85*4882a593Smuzhiyun 	state->pllsel &= ~(PLLSEL_TV_CRTC1_MASK | PLLSEL_TV_CRTC2_MASK);
86*4882a593Smuzhiyun 
87*4882a593Smuzhiyun 	if (mode == DRM_MODE_DPMS_ON) {
88*4882a593Smuzhiyun 		int head = nouveau_crtc(encoder->crtc)->index;
89*4882a593Smuzhiyun 		crtc1A = NVReadVgaCrtc(dev, head, NV_CIO_CRE_RPC1_INDEX);
90*4882a593Smuzhiyun 
91*4882a593Smuzhiyun 		state->pllsel |= head ? PLLSEL_TV_CRTC2_MASK :
92*4882a593Smuzhiyun 					PLLSEL_TV_CRTC1_MASK;
93*4882a593Smuzhiyun 
94*4882a593Smuzhiyun 		/* Inhibit hsync */
95*4882a593Smuzhiyun 		crtc1A |= 0x80;
96*4882a593Smuzhiyun 
97*4882a593Smuzhiyun 		NVWriteVgaCrtc(dev, head, NV_CIO_CRE_RPC1_INDEX, crtc1A);
98*4882a593Smuzhiyun 	}
99*4882a593Smuzhiyun 
100*4882a593Smuzhiyun 	NVWriteRAMDAC(dev, 0, NV_PRAMDAC_PLL_COEFF_SELECT, state->pllsel);
101*4882a593Smuzhiyun 
102*4882a593Smuzhiyun 	get_slave_funcs(encoder)->dpms(encoder, mode);
103*4882a593Smuzhiyun }
104*4882a593Smuzhiyun 
nv04_tv_bind(struct drm_device * dev,int head,bool bind)105*4882a593Smuzhiyun static void nv04_tv_bind(struct drm_device *dev, int head, bool bind)
106*4882a593Smuzhiyun {
107*4882a593Smuzhiyun 	struct nv04_crtc_reg *state = &nv04_display(dev)->mode_reg.crtc_reg[head];
108*4882a593Smuzhiyun 
109*4882a593Smuzhiyun 	state->tv_setup = 0;
110*4882a593Smuzhiyun 
111*4882a593Smuzhiyun 	if (bind)
112*4882a593Smuzhiyun 		state->CRTC[NV_CIO_CRE_49] |= 0x10;
113*4882a593Smuzhiyun 	else
114*4882a593Smuzhiyun 		state->CRTC[NV_CIO_CRE_49] &= ~0x10;
115*4882a593Smuzhiyun 
116*4882a593Smuzhiyun 	NVWriteVgaCrtc(dev, head, NV_CIO_CRE_LCD__INDEX,
117*4882a593Smuzhiyun 		       state->CRTC[NV_CIO_CRE_LCD__INDEX]);
118*4882a593Smuzhiyun 	NVWriteVgaCrtc(dev, head, NV_CIO_CRE_49,
119*4882a593Smuzhiyun 		       state->CRTC[NV_CIO_CRE_49]);
120*4882a593Smuzhiyun 	NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_SETUP,
121*4882a593Smuzhiyun 		      state->tv_setup);
122*4882a593Smuzhiyun }
123*4882a593Smuzhiyun 
nv04_tv_prepare(struct drm_encoder * encoder)124*4882a593Smuzhiyun static void nv04_tv_prepare(struct drm_encoder *encoder)
125*4882a593Smuzhiyun {
126*4882a593Smuzhiyun 	struct drm_device *dev = encoder->dev;
127*4882a593Smuzhiyun 	int head = nouveau_crtc(encoder->crtc)->index;
128*4882a593Smuzhiyun 	const struct drm_encoder_helper_funcs *helper = encoder->helper_private;
129*4882a593Smuzhiyun 
130*4882a593Smuzhiyun 	helper->dpms(encoder, DRM_MODE_DPMS_OFF);
131*4882a593Smuzhiyun 
132*4882a593Smuzhiyun 	nv04_dfp_disable(dev, head);
133*4882a593Smuzhiyun 
134*4882a593Smuzhiyun 	if (nv_two_heads(dev))
135*4882a593Smuzhiyun 		nv04_tv_bind(dev, head ^ 1, false);
136*4882a593Smuzhiyun 
137*4882a593Smuzhiyun 	nv04_tv_bind(dev, head, true);
138*4882a593Smuzhiyun }
139*4882a593Smuzhiyun 
nv04_tv_mode_set(struct drm_encoder * encoder,struct drm_display_mode * mode,struct drm_display_mode * adjusted_mode)140*4882a593Smuzhiyun static void nv04_tv_mode_set(struct drm_encoder *encoder,
141*4882a593Smuzhiyun 			     struct drm_display_mode *mode,
142*4882a593Smuzhiyun 			     struct drm_display_mode *adjusted_mode)
143*4882a593Smuzhiyun {
144*4882a593Smuzhiyun 	struct drm_device *dev = encoder->dev;
145*4882a593Smuzhiyun 	struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
146*4882a593Smuzhiyun 	struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index];
147*4882a593Smuzhiyun 
148*4882a593Smuzhiyun 	regp->tv_htotal = adjusted_mode->htotal;
149*4882a593Smuzhiyun 	regp->tv_vtotal = adjusted_mode->vtotal;
150*4882a593Smuzhiyun 
151*4882a593Smuzhiyun 	/* These delay the TV signals with respect to the VGA port,
152*4882a593Smuzhiyun 	 * they might be useful if we ever allow a CRTC to drive
153*4882a593Smuzhiyun 	 * multiple outputs.
154*4882a593Smuzhiyun 	 */
155*4882a593Smuzhiyun 	regp->tv_hskew = 1;
156*4882a593Smuzhiyun 	regp->tv_hsync_delay = 1;
157*4882a593Smuzhiyun 	regp->tv_hsync_delay2 = 64;
158*4882a593Smuzhiyun 	regp->tv_vskew = 1;
159*4882a593Smuzhiyun 	regp->tv_vsync_delay = 1;
160*4882a593Smuzhiyun 
161*4882a593Smuzhiyun 	get_slave_funcs(encoder)->mode_set(encoder, mode, adjusted_mode);
162*4882a593Smuzhiyun }
163*4882a593Smuzhiyun 
nv04_tv_commit(struct drm_encoder * encoder)164*4882a593Smuzhiyun static void nv04_tv_commit(struct drm_encoder *encoder)
165*4882a593Smuzhiyun {
166*4882a593Smuzhiyun 	struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
167*4882a593Smuzhiyun 	struct drm_device *dev = encoder->dev;
168*4882a593Smuzhiyun 	struct nouveau_drm *drm = nouveau_drm(dev);
169*4882a593Smuzhiyun 	struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
170*4882a593Smuzhiyun 	const struct drm_encoder_helper_funcs *helper = encoder->helper_private;
171*4882a593Smuzhiyun 
172*4882a593Smuzhiyun 	helper->dpms(encoder, DRM_MODE_DPMS_ON);
173*4882a593Smuzhiyun 
174*4882a593Smuzhiyun 	NV_DEBUG(drm, "Output %s is running on CRTC %d using output %c\n",
175*4882a593Smuzhiyun 		 nv04_encoder_get_connector(nv_encoder)->base.name,
176*4882a593Smuzhiyun 		 nv_crtc->index, '@' + ffs(nv_encoder->dcb->or));
177*4882a593Smuzhiyun }
178*4882a593Smuzhiyun 
nv04_tv_destroy(struct drm_encoder * encoder)179*4882a593Smuzhiyun static void nv04_tv_destroy(struct drm_encoder *encoder)
180*4882a593Smuzhiyun {
181*4882a593Smuzhiyun 	get_slave_funcs(encoder)->destroy(encoder);
182*4882a593Smuzhiyun 	drm_encoder_cleanup(encoder);
183*4882a593Smuzhiyun 
184*4882a593Smuzhiyun 	kfree(encoder->helper_private);
185*4882a593Smuzhiyun 	kfree(nouveau_encoder(encoder));
186*4882a593Smuzhiyun }
187*4882a593Smuzhiyun 
188*4882a593Smuzhiyun static const struct drm_encoder_funcs nv04_tv_funcs = {
189*4882a593Smuzhiyun 	.destroy = nv04_tv_destroy,
190*4882a593Smuzhiyun };
191*4882a593Smuzhiyun 
192*4882a593Smuzhiyun static const struct drm_encoder_helper_funcs nv04_tv_helper_funcs = {
193*4882a593Smuzhiyun 	.dpms = nv04_tv_dpms,
194*4882a593Smuzhiyun 	.mode_fixup = drm_i2c_encoder_mode_fixup,
195*4882a593Smuzhiyun 	.prepare = nv04_tv_prepare,
196*4882a593Smuzhiyun 	.commit = nv04_tv_commit,
197*4882a593Smuzhiyun 	.mode_set = nv04_tv_mode_set,
198*4882a593Smuzhiyun 	.detect = drm_i2c_encoder_detect,
199*4882a593Smuzhiyun };
200*4882a593Smuzhiyun 
201*4882a593Smuzhiyun int
nv04_tv_create(struct drm_connector * connector,struct dcb_output * entry)202*4882a593Smuzhiyun nv04_tv_create(struct drm_connector *connector, struct dcb_output *entry)
203*4882a593Smuzhiyun {
204*4882a593Smuzhiyun 	struct nouveau_encoder *nv_encoder;
205*4882a593Smuzhiyun 	struct drm_encoder *encoder;
206*4882a593Smuzhiyun 	struct drm_device *dev = connector->dev;
207*4882a593Smuzhiyun 	struct nouveau_drm *drm = nouveau_drm(dev);
208*4882a593Smuzhiyun 	struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device);
209*4882a593Smuzhiyun 	struct nvkm_i2c_bus *bus = nvkm_i2c_bus_find(i2c, entry->i2c_index);
210*4882a593Smuzhiyun 	int type, ret;
211*4882a593Smuzhiyun 
212*4882a593Smuzhiyun 	/* Ensure that we can talk to this encoder */
213*4882a593Smuzhiyun 	type = nv04_tv_identify(dev, entry->i2c_index);
214*4882a593Smuzhiyun 	if (type < 0)
215*4882a593Smuzhiyun 		return type;
216*4882a593Smuzhiyun 
217*4882a593Smuzhiyun 	/* Allocate the necessary memory */
218*4882a593Smuzhiyun 	nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
219*4882a593Smuzhiyun 	if (!nv_encoder)
220*4882a593Smuzhiyun 		return -ENOMEM;
221*4882a593Smuzhiyun 
222*4882a593Smuzhiyun 	/* Initialize the common members */
223*4882a593Smuzhiyun 	encoder = to_drm_encoder(nv_encoder);
224*4882a593Smuzhiyun 
225*4882a593Smuzhiyun 	drm_encoder_init(dev, encoder, &nv04_tv_funcs, DRM_MODE_ENCODER_TVDAC,
226*4882a593Smuzhiyun 			 NULL);
227*4882a593Smuzhiyun 	drm_encoder_helper_add(encoder, &nv04_tv_helper_funcs);
228*4882a593Smuzhiyun 
229*4882a593Smuzhiyun 	nv_encoder->enc_save = drm_i2c_encoder_save;
230*4882a593Smuzhiyun 	nv_encoder->enc_restore = drm_i2c_encoder_restore;
231*4882a593Smuzhiyun 
232*4882a593Smuzhiyun 	encoder->possible_crtcs = entry->heads;
233*4882a593Smuzhiyun 	encoder->possible_clones = 0;
234*4882a593Smuzhiyun 	nv_encoder->dcb = entry;
235*4882a593Smuzhiyun 	nv_encoder->or = ffs(entry->or) - 1;
236*4882a593Smuzhiyun 
237*4882a593Smuzhiyun 	/* Run the slave-specific initialization */
238*4882a593Smuzhiyun 	ret = drm_i2c_encoder_init(dev, to_encoder_slave(encoder),
239*4882a593Smuzhiyun 				   &bus->i2c,
240*4882a593Smuzhiyun 				   &nv04_tv_encoder_info[type].dev);
241*4882a593Smuzhiyun 	if (ret < 0)
242*4882a593Smuzhiyun 		goto fail_cleanup;
243*4882a593Smuzhiyun 
244*4882a593Smuzhiyun 	/* Attach it to the specified connector. */
245*4882a593Smuzhiyun 	get_slave_funcs(encoder)->create_resources(encoder, connector);
246*4882a593Smuzhiyun 	drm_connector_attach_encoder(connector, encoder);
247*4882a593Smuzhiyun 
248*4882a593Smuzhiyun 	return 0;
249*4882a593Smuzhiyun 
250*4882a593Smuzhiyun fail_cleanup:
251*4882a593Smuzhiyun 	drm_encoder_cleanup(encoder);
252*4882a593Smuzhiyun 	kfree(nv_encoder);
253*4882a593Smuzhiyun 	return ret;
254*4882a593Smuzhiyun }
255