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/OK3568_Linux_fs/kernel/Documentation/kbuild/
H A DKconfig.recursion-issue-0113 # * What values are possible for CORE?
15 # CORE_BELL_A_ADVANCED selects CORE, which means that it influences the values
16 # that are possible for CORE. So for example if CORE_BELL_A_ADVANCED is 'y',
17 # CORE must be 'y' too.
27 # CORE_BELL_A depends on CORE, so CORE influences CORE_BELL_A.
30 # what values are possible for CORE we ended up needing to address questions
31 # regarding possible values of CORE itself again. Answering the original
32 # question of what are the possible values of CORE would make the kconfig
38 # of the "select CORE" from CORE_BELL_A_ADVANCED as that is implicit already
39 # since CORE_BELL_A depends on CORE. Recursive dependency issues are not always
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H A DKconfig.recursion-issue-0225 # have. Let's assume we have some CORE functionality, then the kernel has a
32 # with CORE, one uses "depends on" while the other uses "select". Another
38 # To fix this the "depends on CORE" must be changed to "select CORE", or the
39 # "select CORE" must be changed to "depends on CORE".
49 config CORE config
54 depends on CORE
63 select CORE
/OK3568_Linux_fs/kernel/drivers/net/wireless/mediatek/mt76/mt76x0/
H A Dinitvals_init.h87 { MT_BBP(CORE, 1), 0x00000002 },
88 { MT_BBP(CORE, 4), 0x00000000 },
89 { MT_BBP(CORE, 24), 0x00000000 },
90 { MT_BBP(CORE, 32), 0x4003000a },
91 { MT_BBP(CORE, 42), 0x00000000 },
92 { MT_BBP(CORE, 44), 0x00000000 },
H A Dphy.c191 val = mt76_rr(dev, MT_BBP(CORE, 0)); in mt76x0_phy_wait_bbp_ready()
516 mt76_set(dev, MT_BBP(CORE, 4), BIT(0)); in mt76x0_phy_tssi_dc_calibrate()
518 mt76_clear(dev, MT_BBP(CORE, 4), BIT(0)); in mt76x0_phy_tssi_dc_calibrate()
521 mt76_wr(dev, MT_BBP(CORE, 34), val); in mt76x0_phy_tssi_dc_calibrate()
526 mt76_poll_msec(dev, MT_BBP(CORE, 34), BIT(4), 0, 200); in mt76x0_phy_tssi_dc_calibrate()
527 dev->cal.tssi_dc = mt76_rr(dev, MT_BBP(CORE, 35)) & 0xff; in mt76x0_phy_tssi_dc_calibrate()
534 mt76_set(dev, MT_BBP(CORE, 4), BIT(0)); in mt76x0_phy_tssi_dc_calibrate()
536 mt76_clear(dev, MT_BBP(CORE, 4), BIT(0)); in mt76x0_phy_tssi_dc_calibrate()
550 mt76_wr(dev, MT_BBP(CORE, 34), val); in mt76x0_phy_tssi_adc_calibrate()
552 if (!mt76_poll_msec(dev, MT_BBP(CORE, 34), BIT(4), 0, 200)) { in mt76x0_phy_tssi_adc_calibrate()
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/OK3568_Linux_fs/u-boot/doc/
H A DREADME.mpc85xxcds146 SW3=XX00XXXX == CORE:CCB 2:1
147 XX01XXXX == CORE:CCB 5:2
148 XX10XXXX == CORE:CCB 3:1
149 XX11XXXX == CORE:CCB 7:2
176 SW3=X000XXXX == CORE:CCB 4:1
177 X001XXXX == CORE:CCB 9:2
178 X010XXXX == CORE:CCB 1:1
179 X011XXXX == CORE:CCB 3:2
180 X100XXXX == CORE:CCB 2:1
181 X101XXXX == CORE:CCB 5:2
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/OK3568_Linux_fs/kernel/drivers/net/wireless/mediatek/mt76/mt76x2/
H A Dmac.c37 mt76_set(dev, MT_BBP(CORE, 4), BIT(1)); in mt76x2_mac_stop()
38 mt76_clear(dev, MT_BBP(CORE, 4), BIT(1)); in mt76x2_mac_stop()
40 mt76_set(dev, MT_BBP(CORE, 4), BIT(0)); in mt76x2_mac_stop()
41 mt76_clear(dev, MT_BBP(CORE, 4), BIT(0)); in mt76x2_mac_stop()
H A Dpci_phy.c83 mt76_rmw_field(dev, MT_BBP(CORE, 32), GENMASK(21, 20), 2); in mt76x2_phy_set_antenna()
85 mt76_rmw_field(dev, MT_BBP(CORE, 33), GENMASK(12, 9), 4); in mt76x2_phy_set_antenna()
94 mt76_rmw_field(dev, MT_BBP(CORE, 32), GENMASK(21, 20), 1); in mt76x2_phy_set_antenna()
96 mt76_rmw_field(dev, MT_BBP(CORE, 33), GENMASK(12, 9), 1); in mt76x2_phy_set_antenna()
107 mt76_clear(dev, MT_BBP(CORE, 32), GENMASK(21, 20)); in mt76x2_phy_set_antenna()
108 mt76_clear(dev, MT_BBP(CORE, 33), GENMASK(12, 9)); in mt76x2_phy_set_antenna()
H A Dusb_mac.c143 mt76_set(dev, MT_BBP(CORE, 4), BIT(1)); in mt76x2u_mac_stop()
144 mt76_clear(dev, MT_BBP(CORE, 4), BIT(1)); in mt76x2u_mac_stop()
146 mt76_set(dev, MT_BBP(CORE, 4), BIT(0)); in mt76x2u_mac_stop()
147 mt76_clear(dev, MT_BBP(CORE, 4), BIT(0)); in mt76x2u_mac_stop()
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/regulator/
H A Dnvidia,tegra-regulators-coupling.txt11 On Tegra20 SoC's there are 3 coupled regulators: CORE, RTC and CPU.
12 The CORE and RTC voltages shall be in a range of 170mV from each other
18 On Tegra30 SoC's there are 2 coupled regulators: CORE and CPU. The CORE
19 and CPU voltages shall be in a range of 300mV from each other and CORE
/OK3568_Linux_fs/u-boot/board/freescale/mpc8641hpcn/
H A DREADME24 SW1(1-5) = 01100 CONFIG_SYS_COREPLL = 01000 :: CORE = 2:1
25 01100 :: CORE = 2.5:1
26 10000 :: CORE = 3:1
27 11100 :: CORE = 3.5:1
28 10100 :: CORE = 4:1
29 01110 :: CORE = 4.5:1
/OK3568_Linux_fs/external/xserver/test/
H A Dinput.c167 param.grabtype = CORE; in dix_check_grab_values()
582 a.grabtype = CORE; in dix_grab_matching()
597 b.grabtype = CORE; in dix_grab_matching()
658 a.grabtype = CORE; in dix_grab_matching()
659 b.grabtype = CORE; in dix_grab_matching()
678 a.grabtype = CORE; in dix_grab_matching()
679 b.grabtype = CORE; in dix_grab_matching()
701 a.grabtype = CORE; in dix_grab_matching()
702 b.grabtype = CORE; in dix_grab_matching()
743 a.grabtype = CORE; in dix_grab_matching()
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/OK3568_Linux_fs/yocto/meta-openembedded/meta-networking/recipes-protocols/net-snmp/net-snmp/
H A D0004-configure-fix-incorrect-variable.patch24 …(MAKE) LD_RUN_PATH="$(libdir):`$(PERL) -e 'use Config; print qq($$Config{archlibexp}/CORE);'`") ; \
25 …E) LD_RUN_PATH="$(libdir):`$(PERL) -e 'use Config; print qq($$Config{installprivlib}/CORE);'`") ; \
/OK3568_Linux_fs/kernel/drivers/infiniband/hw/hfi1/
H A Dchip_registers.h51 #define CORE 0x000000000000 macro
52 #define CCE (CORE + 0x000000000000)
53 #define ASIC (CORE + 0x000000400000)
54 #define MISC (CORE + 0x000000500000)
55 #define DC_TOP_CSRS (CORE + 0x000000600000)
56 #define CHIP_DEBUG (CORE + 0x000000700000)
57 #define RXE (CORE + 0x000001000000)
58 #define TXE (CORE + 0x000001800000)
/OK3568_Linux_fs/external/xserver/dix/
H A Dregistry.c34 #define CORE "X11" macro
234 return retval ? retval + sizeof(CORE) : XREGISTRY_UNKNOWN; in LookupMajorName()
346 ExtensionEntry extEntry = { .name = CORE }; in dixResetRegistry()
H A Dgrabs.c86 ((grab->grabtype == CORE) ? "core" : "xi1"), dev->name, dev->id); in PrintDeviceGrabInfo()
124 if (grab->grabtype == CORE) { in PrintDeviceGrabInfo()
227 if (grabtype == CORE || grabtype == XI) in CreateGrab()
536 if (GrabMatchesSecond(pGrab, grab, (pGrab->grabtype == CORE))) { in AddPassiveGrabToList()
618 || !GrabMatchesSecond(grab, pMinuendGrab, (grab->grabtype == CORE))) in DeletePassiveGrabFromList()
H A Devents.c1486 if (grab->grabtype == CORE || grab->grabtype == XI || in UpdateTouchesForGrab()
1579 if (grab->grabtype == CORE || grab->grabtype == XI || in DeactivatePointerGrab()
2044 grabtype = CORE; in ActivateImplicitGrab()
2678 case CORE: in DeliverOneEvent()
2746 DeliverOneEvent(event, dev, CORE, pWin, child, grab); in DeliverDeviceEvents()
3673 if (grab->grabtype == XI || grab->grabtype == CORE) { in ActivatePassiveGrab()
3678 if (grab->grabtype == CORE) in ActivatePassiveGrab()
3688 if (grab->grabtype == CORE) { in ActivatePassiveGrab()
3745 if (othergrab && othergrab->grabtype == CORE && in CoreGrabInterferes()
3798 case CORE: in MatchForType()
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/OK3568_Linux_fs/kernel/drivers/cpufreq/
H A Dimx-cpufreq-dt.c39 CORE, enumerator
73 clk_set_parent(imx7ulp_clks[ARM].clk, imx7ulp_clks[CORE].clk); in imx7ulp_target_intermediate()
/OK3568_Linux_fs/prebuilts/gcc/linux-x86/aarch64/gcc-arm-10.3-2021.07-x86_64-aarch64-none-linux-gnu/lib/gcc/aarch64-none-linux-gnu/10.3.1/plugin/include/config/aarch64/
H A Daarch64-arches.def22 AARCH64_ARCH(NAME, CORE, ARCH_IDENT, ARCH_REV, FLAGS)
25 constant. The CORE is the identifier for a core representative of
H A Daarch64-opts.h39 #define AARCH64_ARCH(NAME, CORE, ARCH_IDENT, ARCH_REV, FLAGS) \ argument
/OK3568_Linux_fs/yocto/poky/meta/recipes-devtools/perl/
H A Dperl_5.34.1.bb143 dir=$(echo ${D}/${libdir}/perl5/${PV}/*/CORE)
159 rm ${D}${libdir}/perl5/${PV}/${TARGET_ARCH}-linux/CORE/xconfig.h
203 ${PKGD}${libdir}/perl5/${PV}/${TARGET_ARCH}-linux/CORE/config.h \
204 ${PKGD}${libdir}/perl5/${PV}/${TARGET_ARCH}-linux/CORE/perl.h \
205 ${PKGD}${libdir}/perl5/${PV}/${TARGET_ARCH}-linux/CORE/pp.h \
271 FILES:${PN}-staticdev:append = " ${libdir}/perl5/${PV}/*/CORE/libperl.a"
273 FILES:${PN}-dev:append = " ${libdir}/perl5/${PV}/*/CORE"
/OK3568_Linux_fs/yocto/poky/meta/recipes-kernel/perf/
H A Dperf-perl.inc5 export PERL_INC = "${STAGING_LIBDIR}${PERL_OWN_DIR}/perl/${@get_perl_version(d)}/CORE"
/OK3568_Linux_fs/u-boot/include/power/
H A Dtps65910.h13 #define CORE 1 macro
/OK3568_Linux_fs/yocto/poky/scripts/lib/checklayer/cases/
H A Ddistro.py14 if self.tc.layer['type'] not in (LayerType.DISTRO, LayerType.CORE):
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/mfd/
H A Drk1000-core.txt3 The RK1000-CORE are RK1000 control register block.
/OK3568_Linux_fs/u-boot/board/siemens/pxm2/
H A Dboard.c91 #define CORE 1 macro
158 voltage_update(CORE, PMIC_OP_REG_SEL_1_1_3)) { in spl_siemens_board_init()

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