1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2011-2013 3*4882a593Smuzhiyun * Texas Instruments, <www.ti.com> 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * For more details, please see the TRM at http://www.ti.com/product/tps65910 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun #ifndef __POWER_TPS65910_H__ 10*4882a593Smuzhiyun #define __POWER_TPS65910_H__ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #define MPU 0 13*4882a593Smuzhiyun #define CORE 1 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #define TPS65910_SR_I2C_ADDR 0x12 16*4882a593Smuzhiyun #define TPS65910_CTRL_I2C_ADDR 0x2D 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun /* PMIC Register offsets */ 19*4882a593Smuzhiyun enum { 20*4882a593Smuzhiyun TPS65910_VDD1_REG = 0x21, 21*4882a593Smuzhiyun TPS65910_VDD1_OP_REG = 0x22, 22*4882a593Smuzhiyun TPS65910_VDD2_REG = 0x24, 23*4882a593Smuzhiyun TPS65910_VDD2_OP_REG = 0x25, 24*4882a593Smuzhiyun TPS65910_DEVCTRL_REG = 0x3F, 25*4882a593Smuzhiyun }; 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun /* VDD2 & VDD1 control register (VDD2_REG & VDD1_REG) */ 28*4882a593Smuzhiyun #define TPS65910_VGAIN_SEL_MASK (0x3 << 6) 29*4882a593Smuzhiyun #define TPS65910_ILMAX_MASK (0x1 << 5) 30*4882a593Smuzhiyun #define TPS65910_TSTEP_MASK (0x7 << 2) 31*4882a593Smuzhiyun #define TPS65910_ST_MASK (0x3) 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun #define TPS65910_REG_VGAIN_SEL_X1 (0x0 << 6) 34*4882a593Smuzhiyun #define TPS65910_REG_VGAIN_SEL_X1_0 (0x1 << 6) 35*4882a593Smuzhiyun #define TPS65910_REG_VGAIN_SEL_X3 (0x2 << 6) 36*4882a593Smuzhiyun #define TPS65910_REG_VGAIN_SEL_X4 (0x3 << 6) 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun #define TPS65910_REG_ILMAX_1_0_A (0x0 << 5) 39*4882a593Smuzhiyun #define TPS65910_REG_ILMAX_1_5_A (0x1 << 5) 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun #define TPS65910_REG_TSTEP_ (0x0 << 2) 42*4882a593Smuzhiyun #define TPS65910_REG_TSTEP_12_5 (0x1 << 2) 43*4882a593Smuzhiyun #define TPS65910_REG_TSTEP_9_4 (0x2 << 2) 44*4882a593Smuzhiyun #define TPS65910_REG_TSTEP_7_5 (0x3 << 2) 45*4882a593Smuzhiyun #define TPS65910_REG_TSTEP_6_25 (0x4 << 2) 46*4882a593Smuzhiyun #define TPS65910_REG_TSTEP_4_7 (0x5 << 2) 47*4882a593Smuzhiyun #define TPS65910_REG_TSTEP_3_12 (0x6 << 2) 48*4882a593Smuzhiyun #define TPS65910_REG_TSTEP_2_5 (0x7 << 2) 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun #define TPS65910_REG_ST_OFF (0x0) 51*4882a593Smuzhiyun #define TPS65910_REG_ST_ON_HI_POW (0x1) 52*4882a593Smuzhiyun #define TPS65910_REG_ST_OFF_1 (0x2) 53*4882a593Smuzhiyun #define TPS65910_REG_ST_ON_LOW_POW (0x3) 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun /* VDD2 & VDD1 voltage selection register. (VDD2_OP_REG & VDD1_OP_REG) */ 57*4882a593Smuzhiyun #define TPS65910_OP_REG_SEL (0x7F) 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun #define TPS65910_OP_REG_CMD_MASK (0x1 << 7) 60*4882a593Smuzhiyun #define TPS65910_OP_REG_CMD_OP (0x0 << 7) 61*4882a593Smuzhiyun #define TPS65910_OP_REG_CMD_SR (0x1 << 7) 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun #define TPS65910_OP_REG_SEL_MASK (0x7F) 64*4882a593Smuzhiyun #define TPS65910_OP_REG_SEL_0_9_5 (0x1F) /* 0.9500 V */ 65*4882a593Smuzhiyun #define TPS65910_OP_REG_SEL_1_1_0 (0x2B) /* 1.1000 V */ 66*4882a593Smuzhiyun #define TPS65910_OP_REG_SEL_1_1_3 (0x2E) /* 1.1375 V */ 67*4882a593Smuzhiyun #define TPS65910_OP_REG_SEL_1_2_0 (0x33) /* 1.2000 V */ 68*4882a593Smuzhiyun #define TPS65910_OP_REG_SEL_1_2_6 (0x38) /* 1.2625 V */ 69*4882a593Smuzhiyun #define TPS65910_OP_REG_SEL_1_3_2_5 (0x3D) /* 1.3250 V */ 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun /* Device control register . (DEVCTRL_REG) */ 72*4882a593Smuzhiyun #define TPS65910_DEVCTRL_REG_SR_CTL_I2C_MASK (0x1 << 4) 73*4882a593Smuzhiyun #define TPS65910_DEVCTRL_REG_SR_CTL_I2C_SEL_SR_I2C (0x0 << 4) 74*4882a593Smuzhiyun #define TPS65910_DEVCTRL_REG_SR_CTL_I2C_SEL_CTL_I2C (0x1 << 4) 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun int tps65910_set_i2c_control(void); 77*4882a593Smuzhiyun int tps65910_voltage_update(unsigned int module, unsigned char vddx_op_vol_sel); 78*4882a593Smuzhiyun #endif /* __POWER_TPS65910_H__ */ 79