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Searched refs:CLK_TOP_MUX_MSDC50_0 (Results 1 – 7 of 7) sorted by relevance

/OK3568_Linux_fs/kernel/include/dt-bindings/clock/
H A Dmt6797-clk.h27 #define CLK_TOP_MUX_MSDC50_0 17 macro
H A Dmt8183-clk.h44 #define CLK_TOP_MUX_MSDC50_0 8 macro
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/mediatek/
H A Dmt8183-evb.dts103 assigned-clocks = <&topckgen CLK_TOP_MUX_MSDC50_0>;
H A Dmt8183-kukui.dtsi298 assigned-clocks = <&topckgen CLK_TOP_MUX_MSDC50_0>;
H A Dmt8183.dtsi704 clocks = <&topckgen CLK_TOP_MUX_MSDC50_0>,
/OK3568_Linux_fs/kernel/drivers/clk/mediatek/
H A Dclk-mt6797.c347 MUX_GATE(CLK_TOP_MUX_MSDC50_0, "msdc50_0_sel", msdc50_0_parents,
H A Dclk-mt8183.c580 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_MSDC50_0, "msdc50_0_sel",