1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) 2017 MediaTek Inc. 4*4882a593Smuzhiyun * Author: Kevin Chen <kevin-cw.chen@mediatek.com> 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef _DT_BINDINGS_CLK_MT6797_H 8*4882a593Smuzhiyun #define _DT_BINDINGS_CLK_MT6797_H 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun /* TOPCKGEN */ 11*4882a593Smuzhiyun #define CLK_TOP_MUX_ULPOSC_AXI_CK_MUX_PRE 1 12*4882a593Smuzhiyun #define CLK_TOP_MUX_ULPOSC_AXI_CK_MUX 2 13*4882a593Smuzhiyun #define CLK_TOP_MUX_AXI 3 14*4882a593Smuzhiyun #define CLK_TOP_MUX_MEM 4 15*4882a593Smuzhiyun #define CLK_TOP_MUX_DDRPHYCFG 5 16*4882a593Smuzhiyun #define CLK_TOP_MUX_MM 6 17*4882a593Smuzhiyun #define CLK_TOP_MUX_PWM 7 18*4882a593Smuzhiyun #define CLK_TOP_MUX_VDEC 8 19*4882a593Smuzhiyun #define CLK_TOP_MUX_VENC 9 20*4882a593Smuzhiyun #define CLK_TOP_MUX_MFG 10 21*4882a593Smuzhiyun #define CLK_TOP_MUX_CAMTG 11 22*4882a593Smuzhiyun #define CLK_TOP_MUX_UART 12 23*4882a593Smuzhiyun #define CLK_TOP_MUX_SPI 13 24*4882a593Smuzhiyun #define CLK_TOP_MUX_ULPOSC_SPI_CK_MUX 14 25*4882a593Smuzhiyun #define CLK_TOP_MUX_USB20 15 26*4882a593Smuzhiyun #define CLK_TOP_MUX_MSDC50_0_HCLK 16 27*4882a593Smuzhiyun #define CLK_TOP_MUX_MSDC50_0 17 28*4882a593Smuzhiyun #define CLK_TOP_MUX_MSDC30_1 18 29*4882a593Smuzhiyun #define CLK_TOP_MUX_MSDC30_2 19 30*4882a593Smuzhiyun #define CLK_TOP_MUX_AUDIO 20 31*4882a593Smuzhiyun #define CLK_TOP_MUX_AUD_INTBUS 21 32*4882a593Smuzhiyun #define CLK_TOP_MUX_PMICSPI 22 33*4882a593Smuzhiyun #define CLK_TOP_MUX_SCP 23 34*4882a593Smuzhiyun #define CLK_TOP_MUX_ATB 24 35*4882a593Smuzhiyun #define CLK_TOP_MUX_MJC 25 36*4882a593Smuzhiyun #define CLK_TOP_MUX_DPI0 26 37*4882a593Smuzhiyun #define CLK_TOP_MUX_AUD_1 27 38*4882a593Smuzhiyun #define CLK_TOP_MUX_AUD_2 28 39*4882a593Smuzhiyun #define CLK_TOP_MUX_SSUSB_TOP_SYS 29 40*4882a593Smuzhiyun #define CLK_TOP_MUX_SPM 30 41*4882a593Smuzhiyun #define CLK_TOP_MUX_BSI_SPI 31 42*4882a593Smuzhiyun #define CLK_TOP_MUX_AUDIO_H 32 43*4882a593Smuzhiyun #define CLK_TOP_MUX_ANC_MD32 33 44*4882a593Smuzhiyun #define CLK_TOP_MUX_MFG_52M 34 45*4882a593Smuzhiyun #define CLK_TOP_SYSPLL_CK 35 46*4882a593Smuzhiyun #define CLK_TOP_SYSPLL_D2 36 47*4882a593Smuzhiyun #define CLK_TOP_SYSPLL1_D2 37 48*4882a593Smuzhiyun #define CLK_TOP_SYSPLL1_D4 38 49*4882a593Smuzhiyun #define CLK_TOP_SYSPLL1_D8 39 50*4882a593Smuzhiyun #define CLK_TOP_SYSPLL1_D16 40 51*4882a593Smuzhiyun #define CLK_TOP_SYSPLL_D3 41 52*4882a593Smuzhiyun #define CLK_TOP_SYSPLL_D3_D3 42 53*4882a593Smuzhiyun #define CLK_TOP_SYSPLL2_D2 43 54*4882a593Smuzhiyun #define CLK_TOP_SYSPLL2_D4 44 55*4882a593Smuzhiyun #define CLK_TOP_SYSPLL2_D8 45 56*4882a593Smuzhiyun #define CLK_TOP_SYSPLL_D5 46 57*4882a593Smuzhiyun #define CLK_TOP_SYSPLL3_D2 47 58*4882a593Smuzhiyun #define CLK_TOP_SYSPLL3_D4 48 59*4882a593Smuzhiyun #define CLK_TOP_SYSPLL_D7 49 60*4882a593Smuzhiyun #define CLK_TOP_SYSPLL4_D2 50 61*4882a593Smuzhiyun #define CLK_TOP_SYSPLL4_D4 51 62*4882a593Smuzhiyun #define CLK_TOP_UNIVPLL_CK 52 63*4882a593Smuzhiyun #define CLK_TOP_UNIVPLL_D7 53 64*4882a593Smuzhiyun #define CLK_TOP_UNIVPLL_D26 54 65*4882a593Smuzhiyun #define CLK_TOP_SSUSB_PHY_48M_CK 55 66*4882a593Smuzhiyun #define CLK_TOP_USB_PHY48M_CK 56 67*4882a593Smuzhiyun #define CLK_TOP_UNIVPLL_D2 57 68*4882a593Smuzhiyun #define CLK_TOP_UNIVPLL1_D2 58 69*4882a593Smuzhiyun #define CLK_TOP_UNIVPLL1_D4 59 70*4882a593Smuzhiyun #define CLK_TOP_UNIVPLL1_D8 60 71*4882a593Smuzhiyun #define CLK_TOP_UNIVPLL_D3 61 72*4882a593Smuzhiyun #define CLK_TOP_UNIVPLL2_D2 62 73*4882a593Smuzhiyun #define CLK_TOP_UNIVPLL2_D4 63 74*4882a593Smuzhiyun #define CLK_TOP_UNIVPLL2_D8 64 75*4882a593Smuzhiyun #define CLK_TOP_UNIVPLL_D5 65 76*4882a593Smuzhiyun #define CLK_TOP_UNIVPLL3_D2 66 77*4882a593Smuzhiyun #define CLK_TOP_UNIVPLL3_D4 67 78*4882a593Smuzhiyun #define CLK_TOP_UNIVPLL3_D8 68 79*4882a593Smuzhiyun #define CLK_TOP_ULPOSC_CK_ORG 69 80*4882a593Smuzhiyun #define CLK_TOP_ULPOSC_CK 70 81*4882a593Smuzhiyun #define CLK_TOP_ULPOSC_D2 71 82*4882a593Smuzhiyun #define CLK_TOP_ULPOSC_D3 72 83*4882a593Smuzhiyun #define CLK_TOP_ULPOSC_D4 73 84*4882a593Smuzhiyun #define CLK_TOP_ULPOSC_D8 74 85*4882a593Smuzhiyun #define CLK_TOP_ULPOSC_D10 75 86*4882a593Smuzhiyun #define CLK_TOP_APLL1_CK 76 87*4882a593Smuzhiyun #define CLK_TOP_APLL2_CK 77 88*4882a593Smuzhiyun #define CLK_TOP_MFGPLL_CK 78 89*4882a593Smuzhiyun #define CLK_TOP_MFGPLL_D2 79 90*4882a593Smuzhiyun #define CLK_TOP_IMGPLL_CK 80 91*4882a593Smuzhiyun #define CLK_TOP_IMGPLL_D2 81 92*4882a593Smuzhiyun #define CLK_TOP_IMGPLL_D4 82 93*4882a593Smuzhiyun #define CLK_TOP_CODECPLL_CK 83 94*4882a593Smuzhiyun #define CLK_TOP_CODECPLL_D2 84 95*4882a593Smuzhiyun #define CLK_TOP_VDECPLL_CK 85 96*4882a593Smuzhiyun #define CLK_TOP_TVDPLL_CK 86 97*4882a593Smuzhiyun #define CLK_TOP_TVDPLL_D2 87 98*4882a593Smuzhiyun #define CLK_TOP_TVDPLL_D4 88 99*4882a593Smuzhiyun #define CLK_TOP_TVDPLL_D8 89 100*4882a593Smuzhiyun #define CLK_TOP_TVDPLL_D16 90 101*4882a593Smuzhiyun #define CLK_TOP_MSDCPLL_CK 91 102*4882a593Smuzhiyun #define CLK_TOP_MSDCPLL_D2 92 103*4882a593Smuzhiyun #define CLK_TOP_MSDCPLL_D4 93 104*4882a593Smuzhiyun #define CLK_TOP_MSDCPLL_D8 94 105*4882a593Smuzhiyun #define CLK_TOP_NR 95 106*4882a593Smuzhiyun 107*4882a593Smuzhiyun /* APMIXED_SYS */ 108*4882a593Smuzhiyun #define CLK_APMIXED_MAINPLL 1 109*4882a593Smuzhiyun #define CLK_APMIXED_UNIVPLL 2 110*4882a593Smuzhiyun #define CLK_APMIXED_MFGPLL 3 111*4882a593Smuzhiyun #define CLK_APMIXED_MSDCPLL 4 112*4882a593Smuzhiyun #define CLK_APMIXED_IMGPLL 5 113*4882a593Smuzhiyun #define CLK_APMIXED_TVDPLL 6 114*4882a593Smuzhiyun #define CLK_APMIXED_CODECPLL 7 115*4882a593Smuzhiyun #define CLK_APMIXED_VDECPLL 8 116*4882a593Smuzhiyun #define CLK_APMIXED_APLL1 9 117*4882a593Smuzhiyun #define CLK_APMIXED_APLL2 10 118*4882a593Smuzhiyun #define CLK_APMIXED_NR 11 119*4882a593Smuzhiyun 120*4882a593Smuzhiyun /* INFRA_SYS */ 121*4882a593Smuzhiyun #define CLK_INFRA_PMIC_TMR 1 122*4882a593Smuzhiyun #define CLK_INFRA_PMIC_AP 2 123*4882a593Smuzhiyun #define CLK_INFRA_PMIC_MD 3 124*4882a593Smuzhiyun #define CLK_INFRA_PMIC_CONN 4 125*4882a593Smuzhiyun #define CLK_INFRA_SCP 5 126*4882a593Smuzhiyun #define CLK_INFRA_SEJ 6 127*4882a593Smuzhiyun #define CLK_INFRA_APXGPT 7 128*4882a593Smuzhiyun #define CLK_INFRA_SEJ_13M 8 129*4882a593Smuzhiyun #define CLK_INFRA_ICUSB 9 130*4882a593Smuzhiyun #define CLK_INFRA_GCE 10 131*4882a593Smuzhiyun #define CLK_INFRA_THERM 11 132*4882a593Smuzhiyun #define CLK_INFRA_I2C0 12 133*4882a593Smuzhiyun #define CLK_INFRA_I2C1 13 134*4882a593Smuzhiyun #define CLK_INFRA_I2C2 14 135*4882a593Smuzhiyun #define CLK_INFRA_I2C3 15 136*4882a593Smuzhiyun #define CLK_INFRA_PWM_HCLK 16 137*4882a593Smuzhiyun #define CLK_INFRA_PWM1 17 138*4882a593Smuzhiyun #define CLK_INFRA_PWM2 18 139*4882a593Smuzhiyun #define CLK_INFRA_PWM3 19 140*4882a593Smuzhiyun #define CLK_INFRA_PWM4 20 141*4882a593Smuzhiyun #define CLK_INFRA_PWM 21 142*4882a593Smuzhiyun #define CLK_INFRA_UART0 22 143*4882a593Smuzhiyun #define CLK_INFRA_UART1 23 144*4882a593Smuzhiyun #define CLK_INFRA_UART2 24 145*4882a593Smuzhiyun #define CLK_INFRA_UART3 25 146*4882a593Smuzhiyun #define CLK_INFRA_MD2MD_CCIF_0 26 147*4882a593Smuzhiyun #define CLK_INFRA_MD2MD_CCIF_1 27 148*4882a593Smuzhiyun #define CLK_INFRA_MD2MD_CCIF_2 28 149*4882a593Smuzhiyun #define CLK_INFRA_FHCTL 29 150*4882a593Smuzhiyun #define CLK_INFRA_BTIF 30 151*4882a593Smuzhiyun #define CLK_INFRA_MD2MD_CCIF_3 31 152*4882a593Smuzhiyun #define CLK_INFRA_SPI 32 153*4882a593Smuzhiyun #define CLK_INFRA_MSDC0 33 154*4882a593Smuzhiyun #define CLK_INFRA_MD2MD_CCIF_4 34 155*4882a593Smuzhiyun #define CLK_INFRA_MSDC1 35 156*4882a593Smuzhiyun #define CLK_INFRA_MSDC2 36 157*4882a593Smuzhiyun #define CLK_INFRA_MD2MD_CCIF_5 37 158*4882a593Smuzhiyun #define CLK_INFRA_GCPU 38 159*4882a593Smuzhiyun #define CLK_INFRA_TRNG 39 160*4882a593Smuzhiyun #define CLK_INFRA_AUXADC 40 161*4882a593Smuzhiyun #define CLK_INFRA_CPUM 41 162*4882a593Smuzhiyun #define CLK_INFRA_AP_C2K_CCIF_0 42 163*4882a593Smuzhiyun #define CLK_INFRA_AP_C2K_CCIF_1 43 164*4882a593Smuzhiyun #define CLK_INFRA_CLDMA 44 165*4882a593Smuzhiyun #define CLK_INFRA_DISP_PWM 45 166*4882a593Smuzhiyun #define CLK_INFRA_AP_DMA 46 167*4882a593Smuzhiyun #define CLK_INFRA_DEVICE_APC 47 168*4882a593Smuzhiyun #define CLK_INFRA_L2C_SRAM 48 169*4882a593Smuzhiyun #define CLK_INFRA_CCIF_AP 49 170*4882a593Smuzhiyun #define CLK_INFRA_AUDIO 50 171*4882a593Smuzhiyun #define CLK_INFRA_CCIF_MD 51 172*4882a593Smuzhiyun #define CLK_INFRA_DRAMC_F26M 52 173*4882a593Smuzhiyun #define CLK_INFRA_I2C4 53 174*4882a593Smuzhiyun #define CLK_INFRA_I2C_APPM 54 175*4882a593Smuzhiyun #define CLK_INFRA_I2C_GPUPM 55 176*4882a593Smuzhiyun #define CLK_INFRA_I2C2_IMM 56 177*4882a593Smuzhiyun #define CLK_INFRA_I2C2_ARB 57 178*4882a593Smuzhiyun #define CLK_INFRA_I2C3_IMM 58 179*4882a593Smuzhiyun #define CLK_INFRA_I2C3_ARB 59 180*4882a593Smuzhiyun #define CLK_INFRA_I2C5 60 181*4882a593Smuzhiyun #define CLK_INFRA_SYS_CIRQ 61 182*4882a593Smuzhiyun #define CLK_INFRA_SPI1 62 183*4882a593Smuzhiyun #define CLK_INFRA_DRAMC_B_F26M 63 184*4882a593Smuzhiyun #define CLK_INFRA_ANC_MD32 64 185*4882a593Smuzhiyun #define CLK_INFRA_ANC_MD32_32K 65 186*4882a593Smuzhiyun #define CLK_INFRA_DVFS_SPM1 66 187*4882a593Smuzhiyun #define CLK_INFRA_AES_TOP0 67 188*4882a593Smuzhiyun #define CLK_INFRA_AES_TOP1 68 189*4882a593Smuzhiyun #define CLK_INFRA_SSUSB_BUS 69 190*4882a593Smuzhiyun #define CLK_INFRA_SPI2 70 191*4882a593Smuzhiyun #define CLK_INFRA_SPI3 71 192*4882a593Smuzhiyun #define CLK_INFRA_SPI4 72 193*4882a593Smuzhiyun #define CLK_INFRA_SPI5 73 194*4882a593Smuzhiyun #define CLK_INFRA_IRTX 74 195*4882a593Smuzhiyun #define CLK_INFRA_SSUSB_SYS 75 196*4882a593Smuzhiyun #define CLK_INFRA_SSUSB_REF 76 197*4882a593Smuzhiyun #define CLK_INFRA_AUDIO_26M 77 198*4882a593Smuzhiyun #define CLK_INFRA_AUDIO_26M_PAD_TOP 78 199*4882a593Smuzhiyun #define CLK_INFRA_MODEM_TEMP_SHARE 79 200*4882a593Smuzhiyun #define CLK_INFRA_VAD_WRAP_SOC 80 201*4882a593Smuzhiyun #define CLK_INFRA_DRAMC_CONF 81 202*4882a593Smuzhiyun #define CLK_INFRA_DRAMC_B_CONF 82 203*4882a593Smuzhiyun #define CLK_INFRA_MFG_VCG 83 204*4882a593Smuzhiyun #define CLK_INFRA_13M 84 205*4882a593Smuzhiyun #define CLK_INFRA_NR 85 206*4882a593Smuzhiyun 207*4882a593Smuzhiyun /* IMG_SYS */ 208*4882a593Smuzhiyun #define CLK_IMG_FDVT 1 209*4882a593Smuzhiyun #define CLK_IMG_DPE 2 210*4882a593Smuzhiyun #define CLK_IMG_DIP 3 211*4882a593Smuzhiyun #define CLK_IMG_LARB6 4 212*4882a593Smuzhiyun #define CLK_IMG_NR 5 213*4882a593Smuzhiyun 214*4882a593Smuzhiyun /* MM_SYS */ 215*4882a593Smuzhiyun #define CLK_MM_SMI_COMMON 1 216*4882a593Smuzhiyun #define CLK_MM_SMI_LARB0 2 217*4882a593Smuzhiyun #define CLK_MM_SMI_LARB5 3 218*4882a593Smuzhiyun #define CLK_MM_CAM_MDP 4 219*4882a593Smuzhiyun #define CLK_MM_MDP_RDMA0 5 220*4882a593Smuzhiyun #define CLK_MM_MDP_RDMA1 6 221*4882a593Smuzhiyun #define CLK_MM_MDP_RSZ0 7 222*4882a593Smuzhiyun #define CLK_MM_MDP_RSZ1 8 223*4882a593Smuzhiyun #define CLK_MM_MDP_RSZ2 9 224*4882a593Smuzhiyun #define CLK_MM_MDP_TDSHP 10 225*4882a593Smuzhiyun #define CLK_MM_MDP_COLOR 11 226*4882a593Smuzhiyun #define CLK_MM_MDP_WDMA 12 227*4882a593Smuzhiyun #define CLK_MM_MDP_WROT0 13 228*4882a593Smuzhiyun #define CLK_MM_MDP_WROT1 14 229*4882a593Smuzhiyun #define CLK_MM_FAKE_ENG 15 230*4882a593Smuzhiyun #define CLK_MM_DISP_OVL0 16 231*4882a593Smuzhiyun #define CLK_MM_DISP_OVL1 17 232*4882a593Smuzhiyun #define CLK_MM_DISP_OVL0_2L 18 233*4882a593Smuzhiyun #define CLK_MM_DISP_OVL1_2L 19 234*4882a593Smuzhiyun #define CLK_MM_DISP_RDMA0 20 235*4882a593Smuzhiyun #define CLK_MM_DISP_RDMA1 21 236*4882a593Smuzhiyun #define CLK_MM_DISP_WDMA0 22 237*4882a593Smuzhiyun #define CLK_MM_DISP_WDMA1 23 238*4882a593Smuzhiyun #define CLK_MM_DISP_COLOR 24 239*4882a593Smuzhiyun #define CLK_MM_DISP_CCORR 25 240*4882a593Smuzhiyun #define CLK_MM_DISP_AAL 26 241*4882a593Smuzhiyun #define CLK_MM_DISP_GAMMA 27 242*4882a593Smuzhiyun #define CLK_MM_DISP_OD 28 243*4882a593Smuzhiyun #define CLK_MM_DISP_DITHER 29 244*4882a593Smuzhiyun #define CLK_MM_DISP_UFOE 30 245*4882a593Smuzhiyun #define CLK_MM_DISP_DSC 31 246*4882a593Smuzhiyun #define CLK_MM_DISP_SPLIT 32 247*4882a593Smuzhiyun #define CLK_MM_DSI0_MM_CLOCK 33 248*4882a593Smuzhiyun #define CLK_MM_DSI1_MM_CLOCK 34 249*4882a593Smuzhiyun #define CLK_MM_DPI_MM_CLOCK 35 250*4882a593Smuzhiyun #define CLK_MM_DPI_INTERFACE_CLOCK 36 251*4882a593Smuzhiyun #define CLK_MM_LARB4_AXI_ASIF_MM_CLOCK 37 252*4882a593Smuzhiyun #define CLK_MM_LARB4_AXI_ASIF_MJC_CLOCK 38 253*4882a593Smuzhiyun #define CLK_MM_DISP_OVL0_MOUT_CLOCK 39 254*4882a593Smuzhiyun #define CLK_MM_FAKE_ENG2 40 255*4882a593Smuzhiyun #define CLK_MM_DSI0_INTERFACE_CLOCK 41 256*4882a593Smuzhiyun #define CLK_MM_DSI1_INTERFACE_CLOCK 42 257*4882a593Smuzhiyun #define CLK_MM_NR 43 258*4882a593Smuzhiyun 259*4882a593Smuzhiyun /* VDEC_SYS */ 260*4882a593Smuzhiyun #define CLK_VDEC_CKEN_ENG 1 261*4882a593Smuzhiyun #define CLK_VDEC_ACTIVE 2 262*4882a593Smuzhiyun #define CLK_VDEC_CKEN 3 263*4882a593Smuzhiyun #define CLK_VDEC_LARB1_CKEN 4 264*4882a593Smuzhiyun #define CLK_VDEC_NR 5 265*4882a593Smuzhiyun 266*4882a593Smuzhiyun /* VENC_SYS */ 267*4882a593Smuzhiyun #define CLK_VENC_0 1 268*4882a593Smuzhiyun #define CLK_VENC_1 2 269*4882a593Smuzhiyun #define CLK_VENC_2 3 270*4882a593Smuzhiyun #define CLK_VENC_3 4 271*4882a593Smuzhiyun #define CLK_VENC_NR 5 272*4882a593Smuzhiyun 273*4882a593Smuzhiyun #endif /* _DT_BINDINGS_CLK_MT6797_H */ 274