1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) 2018 MediaTek Inc. 4*4882a593Smuzhiyun * Author: Weiyi Lu <weiyi.lu@mediatek.com> 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef _DT_BINDINGS_CLK_MT8183_H 8*4882a593Smuzhiyun #define _DT_BINDINGS_CLK_MT8183_H 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun /* APMIXED */ 11*4882a593Smuzhiyun #define CLK_APMIXED_ARMPLL_LL 0 12*4882a593Smuzhiyun #define CLK_APMIXED_ARMPLL_L 1 13*4882a593Smuzhiyun #define CLK_APMIXED_CCIPLL 2 14*4882a593Smuzhiyun #define CLK_APMIXED_MAINPLL 3 15*4882a593Smuzhiyun #define CLK_APMIXED_UNIV2PLL 4 16*4882a593Smuzhiyun #define CLK_APMIXED_MSDCPLL 5 17*4882a593Smuzhiyun #define CLK_APMIXED_MMPLL 6 18*4882a593Smuzhiyun #define CLK_APMIXED_MFGPLL 7 19*4882a593Smuzhiyun #define CLK_APMIXED_TVDPLL 8 20*4882a593Smuzhiyun #define CLK_APMIXED_APLL1 9 21*4882a593Smuzhiyun #define CLK_APMIXED_APLL2 10 22*4882a593Smuzhiyun #define CLK_APMIXED_SSUSB_26M 11 23*4882a593Smuzhiyun #define CLK_APMIXED_APPLL_26M 12 24*4882a593Smuzhiyun #define CLK_APMIXED_MIPIC0_26M 13 25*4882a593Smuzhiyun #define CLK_APMIXED_MDPLLGP_26M 14 26*4882a593Smuzhiyun #define CLK_APMIXED_MMSYS_26M 15 27*4882a593Smuzhiyun #define CLK_APMIXED_UFS_26M 16 28*4882a593Smuzhiyun #define CLK_APMIXED_MIPIC1_26M 17 29*4882a593Smuzhiyun #define CLK_APMIXED_MEMPLL_26M 18 30*4882a593Smuzhiyun #define CLK_APMIXED_CLKSQ_LVPLL_26M 19 31*4882a593Smuzhiyun #define CLK_APMIXED_MIPID0_26M 20 32*4882a593Smuzhiyun #define CLK_APMIXED_MIPID1_26M 21 33*4882a593Smuzhiyun #define CLK_APMIXED_NR_CLK 22 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun /* TOPCKGEN */ 36*4882a593Smuzhiyun #define CLK_TOP_MUX_AXI 0 37*4882a593Smuzhiyun #define CLK_TOP_MUX_MM 1 38*4882a593Smuzhiyun #define CLK_TOP_MUX_CAM 2 39*4882a593Smuzhiyun #define CLK_TOP_MUX_MFG 3 40*4882a593Smuzhiyun #define CLK_TOP_MUX_CAMTG 4 41*4882a593Smuzhiyun #define CLK_TOP_MUX_UART 5 42*4882a593Smuzhiyun #define CLK_TOP_MUX_SPI 6 43*4882a593Smuzhiyun #define CLK_TOP_MUX_MSDC50_0_HCLK 7 44*4882a593Smuzhiyun #define CLK_TOP_MUX_MSDC50_0 8 45*4882a593Smuzhiyun #define CLK_TOP_MUX_MSDC30_1 9 46*4882a593Smuzhiyun #define CLK_TOP_MUX_MSDC30_2 10 47*4882a593Smuzhiyun #define CLK_TOP_MUX_AUDIO 11 48*4882a593Smuzhiyun #define CLK_TOP_MUX_AUD_INTBUS 12 49*4882a593Smuzhiyun #define CLK_TOP_MUX_FPWRAP_ULPOSC 13 50*4882a593Smuzhiyun #define CLK_TOP_MUX_SCP 14 51*4882a593Smuzhiyun #define CLK_TOP_MUX_ATB 15 52*4882a593Smuzhiyun #define CLK_TOP_MUX_SSPM 16 53*4882a593Smuzhiyun #define CLK_TOP_MUX_DPI0 17 54*4882a593Smuzhiyun #define CLK_TOP_MUX_SCAM 18 55*4882a593Smuzhiyun #define CLK_TOP_MUX_AUD_1 19 56*4882a593Smuzhiyun #define CLK_TOP_MUX_AUD_2 20 57*4882a593Smuzhiyun #define CLK_TOP_MUX_DISP_PWM 21 58*4882a593Smuzhiyun #define CLK_TOP_MUX_SSUSB_TOP_XHCI 22 59*4882a593Smuzhiyun #define CLK_TOP_MUX_USB_TOP 23 60*4882a593Smuzhiyun #define CLK_TOP_MUX_SPM 24 61*4882a593Smuzhiyun #define CLK_TOP_MUX_I2C 25 62*4882a593Smuzhiyun #define CLK_TOP_MUX_F52M_MFG 26 63*4882a593Smuzhiyun #define CLK_TOP_MUX_SENINF 27 64*4882a593Smuzhiyun #define CLK_TOP_MUX_DXCC 28 65*4882a593Smuzhiyun #define CLK_TOP_MUX_CAMTG2 29 66*4882a593Smuzhiyun #define CLK_TOP_MUX_AUD_ENG1 30 67*4882a593Smuzhiyun #define CLK_TOP_MUX_AUD_ENG2 31 68*4882a593Smuzhiyun #define CLK_TOP_MUX_FAES_UFSFDE 32 69*4882a593Smuzhiyun #define CLK_TOP_MUX_FUFS 33 70*4882a593Smuzhiyun #define CLK_TOP_MUX_IMG 34 71*4882a593Smuzhiyun #define CLK_TOP_MUX_DSP 35 72*4882a593Smuzhiyun #define CLK_TOP_MUX_DSP1 36 73*4882a593Smuzhiyun #define CLK_TOP_MUX_DSP2 37 74*4882a593Smuzhiyun #define CLK_TOP_MUX_IPU_IF 38 75*4882a593Smuzhiyun #define CLK_TOP_MUX_CAMTG3 39 76*4882a593Smuzhiyun #define CLK_TOP_MUX_CAMTG4 40 77*4882a593Smuzhiyun #define CLK_TOP_MUX_PMICSPI 41 78*4882a593Smuzhiyun #define CLK_TOP_SYSPLL_CK 42 79*4882a593Smuzhiyun #define CLK_TOP_SYSPLL_D2 43 80*4882a593Smuzhiyun #define CLK_TOP_SYSPLL_D3 44 81*4882a593Smuzhiyun #define CLK_TOP_SYSPLL_D5 45 82*4882a593Smuzhiyun #define CLK_TOP_SYSPLL_D7 46 83*4882a593Smuzhiyun #define CLK_TOP_SYSPLL_D2_D2 47 84*4882a593Smuzhiyun #define CLK_TOP_SYSPLL_D2_D4 48 85*4882a593Smuzhiyun #define CLK_TOP_SYSPLL_D2_D8 49 86*4882a593Smuzhiyun #define CLK_TOP_SYSPLL_D2_D16 50 87*4882a593Smuzhiyun #define CLK_TOP_SYSPLL_D3_D2 51 88*4882a593Smuzhiyun #define CLK_TOP_SYSPLL_D3_D4 52 89*4882a593Smuzhiyun #define CLK_TOP_SYSPLL_D3_D8 53 90*4882a593Smuzhiyun #define CLK_TOP_SYSPLL_D5_D2 54 91*4882a593Smuzhiyun #define CLK_TOP_SYSPLL_D5_D4 55 92*4882a593Smuzhiyun #define CLK_TOP_SYSPLL_D7_D2 56 93*4882a593Smuzhiyun #define CLK_TOP_SYSPLL_D7_D4 57 94*4882a593Smuzhiyun #define CLK_TOP_UNIVPLL_CK 58 95*4882a593Smuzhiyun #define CLK_TOP_UNIVPLL_D2 59 96*4882a593Smuzhiyun #define CLK_TOP_UNIVPLL_D3 60 97*4882a593Smuzhiyun #define CLK_TOP_UNIVPLL_D5 61 98*4882a593Smuzhiyun #define CLK_TOP_UNIVPLL_D7 62 99*4882a593Smuzhiyun #define CLK_TOP_UNIVPLL_D2_D2 63 100*4882a593Smuzhiyun #define CLK_TOP_UNIVPLL_D2_D4 64 101*4882a593Smuzhiyun #define CLK_TOP_UNIVPLL_D2_D8 65 102*4882a593Smuzhiyun #define CLK_TOP_UNIVPLL_D3_D2 66 103*4882a593Smuzhiyun #define CLK_TOP_UNIVPLL_D3_D4 67 104*4882a593Smuzhiyun #define CLK_TOP_UNIVPLL_D3_D8 68 105*4882a593Smuzhiyun #define CLK_TOP_UNIVPLL_D5_D2 69 106*4882a593Smuzhiyun #define CLK_TOP_UNIVPLL_D5_D4 70 107*4882a593Smuzhiyun #define CLK_TOP_UNIVPLL_D5_D8 71 108*4882a593Smuzhiyun #define CLK_TOP_APLL1_CK 72 109*4882a593Smuzhiyun #define CLK_TOP_APLL1_D2 73 110*4882a593Smuzhiyun #define CLK_TOP_APLL1_D4 74 111*4882a593Smuzhiyun #define CLK_TOP_APLL1_D8 75 112*4882a593Smuzhiyun #define CLK_TOP_APLL2_CK 76 113*4882a593Smuzhiyun #define CLK_TOP_APLL2_D2 77 114*4882a593Smuzhiyun #define CLK_TOP_APLL2_D4 78 115*4882a593Smuzhiyun #define CLK_TOP_APLL2_D8 79 116*4882a593Smuzhiyun #define CLK_TOP_TVDPLL_CK 80 117*4882a593Smuzhiyun #define CLK_TOP_TVDPLL_D2 81 118*4882a593Smuzhiyun #define CLK_TOP_TVDPLL_D4 82 119*4882a593Smuzhiyun #define CLK_TOP_TVDPLL_D8 83 120*4882a593Smuzhiyun #define CLK_TOP_TVDPLL_D16 84 121*4882a593Smuzhiyun #define CLK_TOP_MSDCPLL_CK 85 122*4882a593Smuzhiyun #define CLK_TOP_MSDCPLL_D2 86 123*4882a593Smuzhiyun #define CLK_TOP_MSDCPLL_D4 87 124*4882a593Smuzhiyun #define CLK_TOP_MSDCPLL_D8 88 125*4882a593Smuzhiyun #define CLK_TOP_MSDCPLL_D16 89 126*4882a593Smuzhiyun #define CLK_TOP_AD_OSC_CK 90 127*4882a593Smuzhiyun #define CLK_TOP_OSC_D2 91 128*4882a593Smuzhiyun #define CLK_TOP_OSC_D4 92 129*4882a593Smuzhiyun #define CLK_TOP_OSC_D8 93 130*4882a593Smuzhiyun #define CLK_TOP_OSC_D16 94 131*4882a593Smuzhiyun #define CLK_TOP_F26M_CK_D2 95 132*4882a593Smuzhiyun #define CLK_TOP_MFGPLL_CK 96 133*4882a593Smuzhiyun #define CLK_TOP_UNIVP_192M_CK 97 134*4882a593Smuzhiyun #define CLK_TOP_UNIVP_192M_D2 98 135*4882a593Smuzhiyun #define CLK_TOP_UNIVP_192M_D4 99 136*4882a593Smuzhiyun #define CLK_TOP_UNIVP_192M_D8 100 137*4882a593Smuzhiyun #define CLK_TOP_UNIVP_192M_D16 101 138*4882a593Smuzhiyun #define CLK_TOP_UNIVP_192M_D32 102 139*4882a593Smuzhiyun #define CLK_TOP_MMPLL_CK 103 140*4882a593Smuzhiyun #define CLK_TOP_MMPLL_D4 104 141*4882a593Smuzhiyun #define CLK_TOP_MMPLL_D4_D2 105 142*4882a593Smuzhiyun #define CLK_TOP_MMPLL_D4_D4 106 143*4882a593Smuzhiyun #define CLK_TOP_MMPLL_D5 107 144*4882a593Smuzhiyun #define CLK_TOP_MMPLL_D5_D2 108 145*4882a593Smuzhiyun #define CLK_TOP_MMPLL_D5_D4 109 146*4882a593Smuzhiyun #define CLK_TOP_MMPLL_D6 110 147*4882a593Smuzhiyun #define CLK_TOP_MMPLL_D7 111 148*4882a593Smuzhiyun #define CLK_TOP_CLK26M 112 149*4882a593Smuzhiyun #define CLK_TOP_CLK13M 113 150*4882a593Smuzhiyun #define CLK_TOP_ULPOSC 114 151*4882a593Smuzhiyun #define CLK_TOP_UNIVP_192M 115 152*4882a593Smuzhiyun #define CLK_TOP_MUX_APLL_I2S0 116 153*4882a593Smuzhiyun #define CLK_TOP_MUX_APLL_I2S1 117 154*4882a593Smuzhiyun #define CLK_TOP_MUX_APLL_I2S2 118 155*4882a593Smuzhiyun #define CLK_TOP_MUX_APLL_I2S3 119 156*4882a593Smuzhiyun #define CLK_TOP_MUX_APLL_I2S4 120 157*4882a593Smuzhiyun #define CLK_TOP_MUX_APLL_I2S5 121 158*4882a593Smuzhiyun #define CLK_TOP_APLL12_DIV0 122 159*4882a593Smuzhiyun #define CLK_TOP_APLL12_DIV1 123 160*4882a593Smuzhiyun #define CLK_TOP_APLL12_DIV2 124 161*4882a593Smuzhiyun #define CLK_TOP_APLL12_DIV3 125 162*4882a593Smuzhiyun #define CLK_TOP_APLL12_DIV4 126 163*4882a593Smuzhiyun #define CLK_TOP_APLL12_DIVB 127 164*4882a593Smuzhiyun #define CLK_TOP_UNIVPLL 128 165*4882a593Smuzhiyun #define CLK_TOP_ARMPLL_DIV_PLL1 129 166*4882a593Smuzhiyun #define CLK_TOP_ARMPLL_DIV_PLL2 130 167*4882a593Smuzhiyun #define CLK_TOP_UNIVPLL_D3_D16 131 168*4882a593Smuzhiyun #define CLK_TOP_NR_CLK 132 169*4882a593Smuzhiyun 170*4882a593Smuzhiyun /* CAMSYS */ 171*4882a593Smuzhiyun #define CLK_CAM_LARB6 0 172*4882a593Smuzhiyun #define CLK_CAM_DFP_VAD 1 173*4882a593Smuzhiyun #define CLK_CAM_CAM 2 174*4882a593Smuzhiyun #define CLK_CAM_CAMTG 3 175*4882a593Smuzhiyun #define CLK_CAM_SENINF 4 176*4882a593Smuzhiyun #define CLK_CAM_CAMSV0 5 177*4882a593Smuzhiyun #define CLK_CAM_CAMSV1 6 178*4882a593Smuzhiyun #define CLK_CAM_CAMSV2 7 179*4882a593Smuzhiyun #define CLK_CAM_CCU 8 180*4882a593Smuzhiyun #define CLK_CAM_LARB3 9 181*4882a593Smuzhiyun #define CLK_CAM_NR_CLK 10 182*4882a593Smuzhiyun 183*4882a593Smuzhiyun /* INFRACFG_AO */ 184*4882a593Smuzhiyun #define CLK_INFRA_PMIC_TMR 0 185*4882a593Smuzhiyun #define CLK_INFRA_PMIC_AP 1 186*4882a593Smuzhiyun #define CLK_INFRA_PMIC_MD 2 187*4882a593Smuzhiyun #define CLK_INFRA_PMIC_CONN 3 188*4882a593Smuzhiyun #define CLK_INFRA_SCPSYS 4 189*4882a593Smuzhiyun #define CLK_INFRA_SEJ 5 190*4882a593Smuzhiyun #define CLK_INFRA_APXGPT 6 191*4882a593Smuzhiyun #define CLK_INFRA_ICUSB 7 192*4882a593Smuzhiyun #define CLK_INFRA_GCE 8 193*4882a593Smuzhiyun #define CLK_INFRA_THERM 9 194*4882a593Smuzhiyun #define CLK_INFRA_I2C0 10 195*4882a593Smuzhiyun #define CLK_INFRA_I2C1 11 196*4882a593Smuzhiyun #define CLK_INFRA_I2C2 12 197*4882a593Smuzhiyun #define CLK_INFRA_I2C3 13 198*4882a593Smuzhiyun #define CLK_INFRA_PWM_HCLK 14 199*4882a593Smuzhiyun #define CLK_INFRA_PWM1 15 200*4882a593Smuzhiyun #define CLK_INFRA_PWM2 16 201*4882a593Smuzhiyun #define CLK_INFRA_PWM3 17 202*4882a593Smuzhiyun #define CLK_INFRA_PWM4 18 203*4882a593Smuzhiyun #define CLK_INFRA_PWM 19 204*4882a593Smuzhiyun #define CLK_INFRA_UART0 20 205*4882a593Smuzhiyun #define CLK_INFRA_UART1 21 206*4882a593Smuzhiyun #define CLK_INFRA_UART2 22 207*4882a593Smuzhiyun #define CLK_INFRA_UART3 23 208*4882a593Smuzhiyun #define CLK_INFRA_GCE_26M 24 209*4882a593Smuzhiyun #define CLK_INFRA_CQ_DMA_FPC 25 210*4882a593Smuzhiyun #define CLK_INFRA_BTIF 26 211*4882a593Smuzhiyun #define CLK_INFRA_SPI0 27 212*4882a593Smuzhiyun #define CLK_INFRA_MSDC0 28 213*4882a593Smuzhiyun #define CLK_INFRA_MSDC1 29 214*4882a593Smuzhiyun #define CLK_INFRA_MSDC2 30 215*4882a593Smuzhiyun #define CLK_INFRA_MSDC0_SCK 31 216*4882a593Smuzhiyun #define CLK_INFRA_DVFSRC 32 217*4882a593Smuzhiyun #define CLK_INFRA_GCPU 33 218*4882a593Smuzhiyun #define CLK_INFRA_TRNG 34 219*4882a593Smuzhiyun #define CLK_INFRA_AUXADC 35 220*4882a593Smuzhiyun #define CLK_INFRA_CPUM 36 221*4882a593Smuzhiyun #define CLK_INFRA_CCIF1_AP 37 222*4882a593Smuzhiyun #define CLK_INFRA_CCIF1_MD 38 223*4882a593Smuzhiyun #define CLK_INFRA_AUXADC_MD 39 224*4882a593Smuzhiyun #define CLK_INFRA_MSDC1_SCK 40 225*4882a593Smuzhiyun #define CLK_INFRA_MSDC2_SCK 41 226*4882a593Smuzhiyun #define CLK_INFRA_AP_DMA 42 227*4882a593Smuzhiyun #define CLK_INFRA_XIU 43 228*4882a593Smuzhiyun #define CLK_INFRA_DEVICE_APC 44 229*4882a593Smuzhiyun #define CLK_INFRA_CCIF_AP 45 230*4882a593Smuzhiyun #define CLK_INFRA_DEBUGSYS 46 231*4882a593Smuzhiyun #define CLK_INFRA_AUDIO 47 232*4882a593Smuzhiyun #define CLK_INFRA_CCIF_MD 48 233*4882a593Smuzhiyun #define CLK_INFRA_DXCC_SEC_CORE 49 234*4882a593Smuzhiyun #define CLK_INFRA_DXCC_AO 50 235*4882a593Smuzhiyun #define CLK_INFRA_DRAMC_F26M 51 236*4882a593Smuzhiyun #define CLK_INFRA_IRTX 52 237*4882a593Smuzhiyun #define CLK_INFRA_DISP_PWM 53 238*4882a593Smuzhiyun #define CLK_INFRA_CLDMA_BCLK 54 239*4882a593Smuzhiyun #define CLK_INFRA_AUDIO_26M_BCLK 55 240*4882a593Smuzhiyun #define CLK_INFRA_SPI1 56 241*4882a593Smuzhiyun #define CLK_INFRA_I2C4 57 242*4882a593Smuzhiyun #define CLK_INFRA_MODEM_TEMP_SHARE 58 243*4882a593Smuzhiyun #define CLK_INFRA_SPI2 59 244*4882a593Smuzhiyun #define CLK_INFRA_SPI3 60 245*4882a593Smuzhiyun #define CLK_INFRA_UNIPRO_SCK 61 246*4882a593Smuzhiyun #define CLK_INFRA_UNIPRO_TICK 62 247*4882a593Smuzhiyun #define CLK_INFRA_UFS_MP_SAP_BCLK 63 248*4882a593Smuzhiyun #define CLK_INFRA_MD32_BCLK 64 249*4882a593Smuzhiyun #define CLK_INFRA_SSPM 65 250*4882a593Smuzhiyun #define CLK_INFRA_UNIPRO_MBIST 66 251*4882a593Smuzhiyun #define CLK_INFRA_SSPM_BUS_HCLK 67 252*4882a593Smuzhiyun #define CLK_INFRA_I2C5 68 253*4882a593Smuzhiyun #define CLK_INFRA_I2C5_ARBITER 69 254*4882a593Smuzhiyun #define CLK_INFRA_I2C5_IMM 70 255*4882a593Smuzhiyun #define CLK_INFRA_I2C1_ARBITER 71 256*4882a593Smuzhiyun #define CLK_INFRA_I2C1_IMM 72 257*4882a593Smuzhiyun #define CLK_INFRA_I2C2_ARBITER 73 258*4882a593Smuzhiyun #define CLK_INFRA_I2C2_IMM 74 259*4882a593Smuzhiyun #define CLK_INFRA_SPI4 75 260*4882a593Smuzhiyun #define CLK_INFRA_SPI5 76 261*4882a593Smuzhiyun #define CLK_INFRA_CQ_DMA 77 262*4882a593Smuzhiyun #define CLK_INFRA_UFS 78 263*4882a593Smuzhiyun #define CLK_INFRA_AES_UFSFDE 79 264*4882a593Smuzhiyun #define CLK_INFRA_UFS_TICK 80 265*4882a593Smuzhiyun #define CLK_INFRA_MSDC0_SELF 81 266*4882a593Smuzhiyun #define CLK_INFRA_MSDC1_SELF 82 267*4882a593Smuzhiyun #define CLK_INFRA_MSDC2_SELF 83 268*4882a593Smuzhiyun #define CLK_INFRA_SSPM_26M_SELF 84 269*4882a593Smuzhiyun #define CLK_INFRA_SSPM_32K_SELF 85 270*4882a593Smuzhiyun #define CLK_INFRA_UFS_AXI 86 271*4882a593Smuzhiyun #define CLK_INFRA_I2C6 87 272*4882a593Smuzhiyun #define CLK_INFRA_AP_MSDC0 88 273*4882a593Smuzhiyun #define CLK_INFRA_MD_MSDC0 89 274*4882a593Smuzhiyun #define CLK_INFRA_USB 90 275*4882a593Smuzhiyun #define CLK_INFRA_DEVMPU_BCLK 91 276*4882a593Smuzhiyun #define CLK_INFRA_CCIF2_AP 92 277*4882a593Smuzhiyun #define CLK_INFRA_CCIF2_MD 93 278*4882a593Smuzhiyun #define CLK_INFRA_CCIF3_AP 94 279*4882a593Smuzhiyun #define CLK_INFRA_CCIF3_MD 95 280*4882a593Smuzhiyun #define CLK_INFRA_SEJ_F13M 96 281*4882a593Smuzhiyun #define CLK_INFRA_AES_BCLK 97 282*4882a593Smuzhiyun #define CLK_INFRA_I2C7 98 283*4882a593Smuzhiyun #define CLK_INFRA_I2C8 99 284*4882a593Smuzhiyun #define CLK_INFRA_FBIST2FPC 100 285*4882a593Smuzhiyun #define CLK_INFRA_NR_CLK 101 286*4882a593Smuzhiyun 287*4882a593Smuzhiyun /* PERICFG */ 288*4882a593Smuzhiyun #define CLK_PERI_AXI 0 289*4882a593Smuzhiyun #define CLK_PERI_NR_CLK 1 290*4882a593Smuzhiyun 291*4882a593Smuzhiyun /* MFGCFG */ 292*4882a593Smuzhiyun #define CLK_MFG_BG3D 0 293*4882a593Smuzhiyun #define CLK_MFG_NR_CLK 1 294*4882a593Smuzhiyun 295*4882a593Smuzhiyun /* IMG */ 296*4882a593Smuzhiyun #define CLK_IMG_OWE 0 297*4882a593Smuzhiyun #define CLK_IMG_WPE_B 1 298*4882a593Smuzhiyun #define CLK_IMG_WPE_A 2 299*4882a593Smuzhiyun #define CLK_IMG_MFB 3 300*4882a593Smuzhiyun #define CLK_IMG_RSC 4 301*4882a593Smuzhiyun #define CLK_IMG_DPE 5 302*4882a593Smuzhiyun #define CLK_IMG_FDVT 6 303*4882a593Smuzhiyun #define CLK_IMG_DIP 7 304*4882a593Smuzhiyun #define CLK_IMG_LARB2 8 305*4882a593Smuzhiyun #define CLK_IMG_LARB5 9 306*4882a593Smuzhiyun #define CLK_IMG_NR_CLK 10 307*4882a593Smuzhiyun 308*4882a593Smuzhiyun /* MMSYS_CONFIG */ 309*4882a593Smuzhiyun #define CLK_MM_SMI_COMMON 0 310*4882a593Smuzhiyun #define CLK_MM_SMI_LARB0 1 311*4882a593Smuzhiyun #define CLK_MM_SMI_LARB1 2 312*4882a593Smuzhiyun #define CLK_MM_GALS_COMM0 3 313*4882a593Smuzhiyun #define CLK_MM_GALS_COMM1 4 314*4882a593Smuzhiyun #define CLK_MM_GALS_CCU2MM 5 315*4882a593Smuzhiyun #define CLK_MM_GALS_IPU12MM 6 316*4882a593Smuzhiyun #define CLK_MM_GALS_IMG2MM 7 317*4882a593Smuzhiyun #define CLK_MM_GALS_CAM2MM 8 318*4882a593Smuzhiyun #define CLK_MM_GALS_IPU2MM 9 319*4882a593Smuzhiyun #define CLK_MM_MDP_DL_TXCK 10 320*4882a593Smuzhiyun #define CLK_MM_IPU_DL_TXCK 11 321*4882a593Smuzhiyun #define CLK_MM_MDP_RDMA0 12 322*4882a593Smuzhiyun #define CLK_MM_MDP_RDMA1 13 323*4882a593Smuzhiyun #define CLK_MM_MDP_RSZ0 14 324*4882a593Smuzhiyun #define CLK_MM_MDP_RSZ1 15 325*4882a593Smuzhiyun #define CLK_MM_MDP_TDSHP 16 326*4882a593Smuzhiyun #define CLK_MM_MDP_WROT0 17 327*4882a593Smuzhiyun #define CLK_MM_FAKE_ENG 18 328*4882a593Smuzhiyun #define CLK_MM_DISP_OVL0 19 329*4882a593Smuzhiyun #define CLK_MM_DISP_OVL0_2L 20 330*4882a593Smuzhiyun #define CLK_MM_DISP_OVL1_2L 21 331*4882a593Smuzhiyun #define CLK_MM_DISP_RDMA0 22 332*4882a593Smuzhiyun #define CLK_MM_DISP_RDMA1 23 333*4882a593Smuzhiyun #define CLK_MM_DISP_WDMA0 24 334*4882a593Smuzhiyun #define CLK_MM_DISP_COLOR0 25 335*4882a593Smuzhiyun #define CLK_MM_DISP_CCORR0 26 336*4882a593Smuzhiyun #define CLK_MM_DISP_AAL0 27 337*4882a593Smuzhiyun #define CLK_MM_DISP_GAMMA0 28 338*4882a593Smuzhiyun #define CLK_MM_DISP_DITHER0 29 339*4882a593Smuzhiyun #define CLK_MM_DISP_SPLIT 30 340*4882a593Smuzhiyun #define CLK_MM_DSI0_MM 31 341*4882a593Smuzhiyun #define CLK_MM_DSI0_IF 32 342*4882a593Smuzhiyun #define CLK_MM_DPI_MM 33 343*4882a593Smuzhiyun #define CLK_MM_DPI_IF 34 344*4882a593Smuzhiyun #define CLK_MM_FAKE_ENG2 35 345*4882a593Smuzhiyun #define CLK_MM_MDP_DL_RX 36 346*4882a593Smuzhiyun #define CLK_MM_IPU_DL_RX 37 347*4882a593Smuzhiyun #define CLK_MM_26M 38 348*4882a593Smuzhiyun #define CLK_MM_MMSYS_R2Y 39 349*4882a593Smuzhiyun #define CLK_MM_DISP_RSZ 40 350*4882a593Smuzhiyun #define CLK_MM_MDP_WDMA0 41 351*4882a593Smuzhiyun #define CLK_MM_MDP_AAL 42 352*4882a593Smuzhiyun #define CLK_MM_MDP_CCORR 43 353*4882a593Smuzhiyun #define CLK_MM_DBI_MM 44 354*4882a593Smuzhiyun #define CLK_MM_DBI_IF 45 355*4882a593Smuzhiyun #define CLK_MM_NR_CLK 46 356*4882a593Smuzhiyun 357*4882a593Smuzhiyun /* VDEC_GCON */ 358*4882a593Smuzhiyun #define CLK_VDEC_VDEC 0 359*4882a593Smuzhiyun #define CLK_VDEC_LARB1 1 360*4882a593Smuzhiyun #define CLK_VDEC_NR_CLK 2 361*4882a593Smuzhiyun 362*4882a593Smuzhiyun /* VENC_GCON */ 363*4882a593Smuzhiyun #define CLK_VENC_LARB 0 364*4882a593Smuzhiyun #define CLK_VENC_VENC 1 365*4882a593Smuzhiyun #define CLK_VENC_JPGENC 2 366*4882a593Smuzhiyun #define CLK_VENC_NR_CLK 3 367*4882a593Smuzhiyun 368*4882a593Smuzhiyun /* AUDIO */ 369*4882a593Smuzhiyun #define CLK_AUDIO_TML 0 370*4882a593Smuzhiyun #define CLK_AUDIO_DAC_PREDIS 1 371*4882a593Smuzhiyun #define CLK_AUDIO_DAC 2 372*4882a593Smuzhiyun #define CLK_AUDIO_ADC 3 373*4882a593Smuzhiyun #define CLK_AUDIO_APLL_TUNER 4 374*4882a593Smuzhiyun #define CLK_AUDIO_APLL2_TUNER 5 375*4882a593Smuzhiyun #define CLK_AUDIO_24M 6 376*4882a593Smuzhiyun #define CLK_AUDIO_22M 7 377*4882a593Smuzhiyun #define CLK_AUDIO_AFE 8 378*4882a593Smuzhiyun #define CLK_AUDIO_I2S4 9 379*4882a593Smuzhiyun #define CLK_AUDIO_I2S3 10 380*4882a593Smuzhiyun #define CLK_AUDIO_I2S2 11 381*4882a593Smuzhiyun #define CLK_AUDIO_I2S1 12 382*4882a593Smuzhiyun #define CLK_AUDIO_PDN_ADDA6_ADC 13 383*4882a593Smuzhiyun #define CLK_AUDIO_TDM 14 384*4882a593Smuzhiyun #define CLK_AUDIO_NR_CLK 15 385*4882a593Smuzhiyun 386*4882a593Smuzhiyun /* IPU_CONN */ 387*4882a593Smuzhiyun #define CLK_IPU_CONN_IPU 0 388*4882a593Smuzhiyun #define CLK_IPU_CONN_AHB 1 389*4882a593Smuzhiyun #define CLK_IPU_CONN_AXI 2 390*4882a593Smuzhiyun #define CLK_IPU_CONN_ISP 3 391*4882a593Smuzhiyun #define CLK_IPU_CONN_CAM_ADL 4 392*4882a593Smuzhiyun #define CLK_IPU_CONN_IMG_ADL 5 393*4882a593Smuzhiyun #define CLK_IPU_CONN_DAP_RX 6 394*4882a593Smuzhiyun #define CLK_IPU_CONN_APB2AXI 7 395*4882a593Smuzhiyun #define CLK_IPU_CONN_APB2AHB 8 396*4882a593Smuzhiyun #define CLK_IPU_CONN_IPU_CAB1TO2 9 397*4882a593Smuzhiyun #define CLK_IPU_CONN_IPU1_CAB1TO2 10 398*4882a593Smuzhiyun #define CLK_IPU_CONN_IPU2_CAB1TO2 11 399*4882a593Smuzhiyun #define CLK_IPU_CONN_CAB3TO3 12 400*4882a593Smuzhiyun #define CLK_IPU_CONN_CAB2TO1 13 401*4882a593Smuzhiyun #define CLK_IPU_CONN_CAB3TO1_SLICE 14 402*4882a593Smuzhiyun #define CLK_IPU_CONN_NR_CLK 15 403*4882a593Smuzhiyun 404*4882a593Smuzhiyun /* IPU_ADL */ 405*4882a593Smuzhiyun #define CLK_IPU_ADL_CABGEN 0 406*4882a593Smuzhiyun #define CLK_IPU_ADL_NR_CLK 1 407*4882a593Smuzhiyun 408*4882a593Smuzhiyun /* IPU_CORE0 */ 409*4882a593Smuzhiyun #define CLK_IPU_CORE0_JTAG 0 410*4882a593Smuzhiyun #define CLK_IPU_CORE0_AXI 1 411*4882a593Smuzhiyun #define CLK_IPU_CORE0_IPU 2 412*4882a593Smuzhiyun #define CLK_IPU_CORE0_NR_CLK 3 413*4882a593Smuzhiyun 414*4882a593Smuzhiyun /* IPU_CORE1 */ 415*4882a593Smuzhiyun #define CLK_IPU_CORE1_JTAG 0 416*4882a593Smuzhiyun #define CLK_IPU_CORE1_AXI 1 417*4882a593Smuzhiyun #define CLK_IPU_CORE1_IPU 2 418*4882a593Smuzhiyun #define CLK_IPU_CORE1_NR_CLK 3 419*4882a593Smuzhiyun 420*4882a593Smuzhiyun /* MCUCFG */ 421*4882a593Smuzhiyun #define CLK_MCU_MP0_SEL 0 422*4882a593Smuzhiyun #define CLK_MCU_MP2_SEL 1 423*4882a593Smuzhiyun #define CLK_MCU_BUS_SEL 2 424*4882a593Smuzhiyun #define CLK_MCU_NR_CLK 3 425*4882a593Smuzhiyun 426*4882a593Smuzhiyun #endif /* _DT_BINDINGS_CLK_MT8183_H */ 427