Searched refs:CLK_SPI_PLL_SEL_MASK (Results 1 – 7 of 7) sorted by relevance
171 CLK_SPI_PLL_SEL_MASK = 1 << CLK_SPI_PLL_SEL_SHIFT, enumerator
422 CLK_SPI_PLL_SEL_MASK = 1, enumerator
240 CLK_SPI_PLL_SEL_MASK = 0x3 << CLK_SPI_PLL_SEL_SHIFT, enumerator
391 mux = (con & CLK_SPI_PLL_SEL_MASK) >> CLK_SPI_PLL_SEL_SHIFT; in rk3328_spi_get_clk()406 CLK_SPI_PLL_SEL_MASK | CLK_SPI_DIV_CON_MASK, in rk3328_spi_set_clk()
789 CLK_SPI_PLL_SEL_MASK << CLK_SPI0_PLL_SEL_SHIFT, in px30_spi_set_clk()796 CLK_SPI_PLL_SEL_MASK << CLK_SPI1_PLL_SEL_SHIFT, in px30_spi_set_clk()
488 CLK_SPI_PLL_SEL_MASK | CLK_SPI_DIV_CON_MASK, in rk3308_spi_set_clk()
261 CLK_SPI_PLL_SEL_MASK = ((1 < CLK_SPI_PLL_SEL_WIDTH) - 1), enumerator