Home
last modified time | relevance | path

Searched refs:AR71XX_PLL_BASE (Results 1 – 9 of 9) sorted by relevance

/OK3568_Linux_fs/u-boot/arch/mips/mach-ath79/
H A Dreset.c78 void __iomem *pregs = map_physmem(AR71XX_PLL_BASE, AR71XX_PLL_SIZE, in eth_init_ar933x()
113 void __iomem *pregs = map_physmem(AR71XX_PLL_BASE, AR71XX_PLL_SIZE, in eth_init_ar934x()
209 void __iomem *pregs = map_physmem(AR71XX_PLL_BASE, AR71XX_PLL_SIZE, in usb_reset_qca953x()
/OK3568_Linux_fs/u-boot/arch/mips/mach-ath79/ar933x/
H A Dlowlevel_init.S158 li t0, CKSEG1ADDR(AR71XX_PLL_BASE)
272 li t0, CKSEG1ADDR(AR71XX_PLL_BASE)
H A Dclk.c37 regs = map_physmem(AR71XX_PLL_BASE, AR71XX_PLL_SIZE, in get_clocks()
/OK3568_Linux_fs/u-boot/arch/mips/mach-ath79/ar934x/
H A Dclk.c108 void __iomem *pll_regs = map_physmem(AR71XX_PLL_BASE, in ar934x_pll_init()
266 regs = map_physmem(AR71XX_PLL_BASE, AR71XX_PLL_SIZE, in ar934x_update_clock()
/OK3568_Linux_fs/u-boot/arch/mips/mach-ath79/qca953x/
H A Dclk.c37 regs = map_physmem(AR71XX_PLL_BASE, AR71XX_PLL_SIZE, in get_clocks()
H A Dlowlevel_init.S135 li t0, CKSEG1ADDR(AR71XX_PLL_BASE)
/OK3568_Linux_fs/kernel/arch/mips/ath79/
H A Dsetup.c229 ath79_pll_base = ioremap(AR71XX_PLL_BASE, in plat_mem_setup()
/OK3568_Linux_fs/u-boot/arch/mips/mach-ath79/include/mach/
H A Dar71xx_regs.h47 #define AR71XX_PLL_BASE \ macro
/OK3568_Linux_fs/kernel/arch/mips/include/asm/mach-ath79/
H A Dar71xx_regs.h39 #define AR71XX_PLL_BASE (AR71XX_APB_BASE + 0x00050000) macro