1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com> 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #include <common.h> 8*4882a593Smuzhiyun #include <asm/io.h> 9*4882a593Smuzhiyun #include <asm/addrspace.h> 10*4882a593Smuzhiyun #include <asm/types.h> 11*4882a593Smuzhiyun #include <mach/ar71xx_regs.h> 12*4882a593Smuzhiyun #include <mach/ath79.h> 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun DECLARE_GLOBAL_DATA_PTR; 15*4882a593Smuzhiyun qca953x_get_xtal(void)16*4882a593Smuzhiyunstatic u32 qca953x_get_xtal(void) 17*4882a593Smuzhiyun { 18*4882a593Smuzhiyun u32 val; 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun val = ath79_get_bootstrap(); 21*4882a593Smuzhiyun if (val & QCA953X_BOOTSTRAP_REF_CLK_40) 22*4882a593Smuzhiyun return 40000000; 23*4882a593Smuzhiyun else 24*4882a593Smuzhiyun return 25000000; 25*4882a593Smuzhiyun } 26*4882a593Smuzhiyun get_serial_clock(void)27*4882a593Smuzhiyunint get_serial_clock(void) 28*4882a593Smuzhiyun { 29*4882a593Smuzhiyun return qca953x_get_xtal(); 30*4882a593Smuzhiyun } 31*4882a593Smuzhiyun get_clocks(void)32*4882a593Smuzhiyunint get_clocks(void) 33*4882a593Smuzhiyun { 34*4882a593Smuzhiyun void __iomem *regs; 35*4882a593Smuzhiyun u32 val, ctrl, xtal, pll, div; 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun regs = map_physmem(AR71XX_PLL_BASE, AR71XX_PLL_SIZE, 38*4882a593Smuzhiyun MAP_NOCACHE); 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun xtal = qca953x_get_xtal(); 41*4882a593Smuzhiyun ctrl = readl(regs + QCA953X_PLL_CLK_CTRL_REG); 42*4882a593Smuzhiyun val = readl(regs + QCA953X_PLL_CPU_CONFIG_REG); 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun /* VCOOUT = XTAL * DIV_INT */ 45*4882a593Smuzhiyun div = (val >> QCA953X_PLL_CPU_CONFIG_REFDIV_SHIFT) 46*4882a593Smuzhiyun & QCA953X_PLL_CPU_CONFIG_REFDIV_MASK; 47*4882a593Smuzhiyun pll = xtal / div; 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun /* PLLOUT = VCOOUT * (1/2^OUTDIV) */ 50*4882a593Smuzhiyun div = (val >> QCA953X_PLL_CPU_CONFIG_NINT_SHIFT) 51*4882a593Smuzhiyun & QCA953X_PLL_CPU_CONFIG_NINT_MASK; 52*4882a593Smuzhiyun pll *= div; 53*4882a593Smuzhiyun div = (val >> QCA953X_PLL_CPU_CONFIG_OUTDIV_SHIFT) 54*4882a593Smuzhiyun & QCA953X_PLL_CPU_CONFIG_OUTDIV_MASK; 55*4882a593Smuzhiyun if (!div) 56*4882a593Smuzhiyun div = 1; 57*4882a593Smuzhiyun pll >>= div; 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun /* CPU_CLK = PLLOUT / CPU_POST_DIV */ 60*4882a593Smuzhiyun div = ((ctrl >> QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) 61*4882a593Smuzhiyun & QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_MASK) + 1; 62*4882a593Smuzhiyun gd->cpu_clk = pll / div; 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun val = readl(regs + QCA953X_PLL_DDR_CONFIG_REG); 66*4882a593Smuzhiyun /* VCOOUT = XTAL * DIV_INT */ 67*4882a593Smuzhiyun div = (val >> QCA953X_PLL_DDR_CONFIG_REFDIV_SHIFT) 68*4882a593Smuzhiyun & QCA953X_PLL_DDR_CONFIG_REFDIV_MASK; 69*4882a593Smuzhiyun pll = xtal / div; 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun /* PLLOUT = VCOOUT * (1/2^OUTDIV) */ 72*4882a593Smuzhiyun div = (val >> QCA953X_PLL_DDR_CONFIG_NINT_SHIFT) 73*4882a593Smuzhiyun & QCA953X_PLL_DDR_CONFIG_NINT_MASK; 74*4882a593Smuzhiyun pll *= div; 75*4882a593Smuzhiyun div = (val >> QCA953X_PLL_DDR_CONFIG_OUTDIV_SHIFT) 76*4882a593Smuzhiyun & QCA953X_PLL_DDR_CONFIG_OUTDIV_MASK; 77*4882a593Smuzhiyun if (!div) 78*4882a593Smuzhiyun div = 1; 79*4882a593Smuzhiyun pll >>= div; 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun /* DDR_CLK = PLLOUT / DDR_POST_DIV */ 82*4882a593Smuzhiyun div = ((ctrl >> QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT) 83*4882a593Smuzhiyun & QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_MASK) + 1; 84*4882a593Smuzhiyun gd->mem_clk = pll / div; 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun div = ((ctrl >> QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT) 87*4882a593Smuzhiyun & QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_MASK) + 1; 88*4882a593Smuzhiyun if (ctrl & QCA953X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL) { 89*4882a593Smuzhiyun /* AHB_CLK = DDR_CLK / AHB_POST_DIV */ 90*4882a593Smuzhiyun gd->bus_clk = gd->mem_clk / (div + 1); 91*4882a593Smuzhiyun } else { 92*4882a593Smuzhiyun /* AHB_CLK = CPU_CLK / AHB_POST_DIV */ 93*4882a593Smuzhiyun gd->bus_clk = gd->cpu_clk / (div + 1); 94*4882a593Smuzhiyun } 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun return 0; 97*4882a593Smuzhiyun } 98*4882a593Smuzhiyun get_bus_freq(ulong dummy)99*4882a593Smuzhiyunulong get_bus_freq(ulong dummy) 100*4882a593Smuzhiyun { 101*4882a593Smuzhiyun if (!gd->bus_clk) 102*4882a593Smuzhiyun get_clocks(); 103*4882a593Smuzhiyun return gd->bus_clk; 104*4882a593Smuzhiyun } 105*4882a593Smuzhiyun get_ddr_freq(ulong dummy)106*4882a593Smuzhiyunulong get_ddr_freq(ulong dummy) 107*4882a593Smuzhiyun { 108*4882a593Smuzhiyun if (!gd->mem_clk) 109*4882a593Smuzhiyun get_clocks(); 110*4882a593Smuzhiyun return gd->mem_clk; 111*4882a593Smuzhiyun } 112