Home
last modified time | relevance | path

Searched refs:i (Results 176 – 200 of 613) sorted by relevance

12345678910>>...25

/rk3399_ARM-atf/plat/xilinx/versal/
H A Dplat_psci.c78 for (size_t i = 0U; i <= PLAT_MAX_PWR_LVL; i++) { in versal_pwr_domain_suspend() local
80 __func__, i, target_state->pwr_domain_state[i]); in versal_pwr_domain_suspend()
119 for (size_t i = 0U; i <= PLAT_MAX_PWR_LVL; i++) { in versal_pwr_domain_suspend_finish() local
121 __func__, i, target_state->pwr_domain_state[i]); in versal_pwr_domain_suspend_finish()
236 for (size_t i = 0U; i <= PLAT_MAX_PWR_LVL; i++) { in versal_pwr_domain_off() local
238 __func__, i, target_state->pwr_domain_state[i]); in versal_pwr_domain_off()
/rk3399_ARM-atf/drivers/nxp/ddr/phy-gen2/
H A Dphy.c102 uint32_t i = 0U; in read_phy_reg() local
104 for (i = 0U; i < len/2; i++) { in read_phy_reg()
105 buf[i] = phy_io_read16(phy, (addr + i)); in read_phy_reg()
132 uint32_t i = 0U; in findmax() local
134 for (i = 0U; i < len; i++) { in findmax()
135 if (buf[i] > max) { in findmax()
136 max = buf[i]; in findmax()
147 uint32_t i, val = 0U; in get_cdd_val() local
155 for (i = 0U; i < NUM_OF_DDRC; i++) { in get_cdd_val()
157 phy = phy_ptr[i]; in get_cdd_val()
[all …]
/rk3399_ARM-atf/plat/st/common/
H A Dstm32mp_fconf_io.c139 unsigned int i; in fconf_populate_stm32mp_io_policies() local
154 for (i = 0U; i < FCONF_ST_IO_UUID_NUMBER; i++) { in fconf_populate_stm32mp_io_policies()
160 err = fdtw_read_uuid(dtb, node, load_info[i].name, 16, in fconf_populate_stm32mp_io_policies()
163 WARN("FCONF: Read cell failed for %s\n", load_info[i].name); in fconf_populate_stm32mp_io_policies()
169 load_info[i].name, in fconf_populate_stm32mp_io_policies()
182 policies[load_info[i].image_id].image_spec = (uintptr_t)uuid_ptr; in fconf_populate_stm32mp_io_policies()
183 switch (load_info[i].image_id) { in fconf_populate_stm32mp_io_policies()
188 policies[load_info[i].image_id].dev_handle = &enc_dev_handle; in fconf_populate_stm32mp_io_policies()
189 policies[load_info[i].image_id].check = open_enc_fip; in fconf_populate_stm32mp_io_policies()
193 policies[load_info[i].image_id].dev_handle = &fip_dev_handle; in fconf_populate_stm32mp_io_policies()
[all …]
/rk3399_ARM-atf/drivers/qti/crypto/
H A Drng.c15 int i = 0; in qti_rng_get_data() local
37 for (i = 0; i < 4; i++) { in qti_rng_get_data()
38 *out = (uint8_t) (tmp_rndm >> (8 * i)); in qti_rng_get_data()
/rk3399_ARM-atf/drivers/rpi3/sdhost/
H A Drpi3_sdhost.c483 for (int i = 0; i < size / 4; i++) { in rpi3_sdhost_read() local
507 i, in rpi3_sdhost_read()
518 buf1[i] = data; in rpi3_sdhost_read()
547 for (int i = 0; i < size / 4; i++) { in rpi3_sdhost_write() local
549 uint32_t data = buf1[i]; in rpi3_sdhost_write()
597 for (int i = 48; i <= 53; i++) { in rpi3_sdhost_init() local
598 rpi3_sdhost_params.gpio48_pinselect[i - 48] in rpi3_sdhost_init()
599 = rpi3_gpio_get_select(i); in rpi3_sdhost_init()
601 i, in rpi3_sdhost_init()
602 rpi3_sdhost_params.gpio48_pinselect[i - 48]); in rpi3_sdhost_init()
[all …]
/rk3399_ARM-atf/plat/socionext/synquacer/
H A Dsq_topology.c32 int i; in plat_get_power_domain_tree_desc() local
36 for (i = 0; i < PLAT_CLUSTER_COUNT; i++) in plat_get_power_domain_tree_desc()
37 sq_pd_tree_desc[i + 1] = PLAT_MAX_CORES_PER_CLUSTER; in plat_get_power_domain_tree_desc()
/rk3399_ARM-atf/plat/socionext/uniphier/
H A Duniphier_topology.c16 int i; in plat_get_power_domain_tree_desc() local
20 for (i = 0; i < UNIPHIER_CLUSTER_COUNT; i++) in plat_get_power_domain_tree_desc()
21 uniphier_power_domain_tree_desc[i + 1] = in plat_get_power_domain_tree_desc()
/rk3399_ARM-atf/drivers/auth/
H A Dauth_mod.c48 int i; in auth_get_param() local
53 for (i = 0 ; i < COT_MAX_VERIFIED_PARAMS ; i++) { in auth_get_param()
55 img_desc->authenticated_data[i].type_desc)) { in auth_get_param()
56 *param = img_desc->authenticated_data[i].data.ptr; in auth_get_param()
57 *len = img_desc->authenticated_data[i].data.len; in auth_get_param()
331 unsigned int data_len, len, i; in auth_nvctr() local
376 for (i = 0; i < len; i++) { in auth_nvctr()
477 int rc, i; in auth_mod_verify_img() local
498 for (i = 0 ; i < AUTH_METHOD_NUM ; i++) { in auth_mod_verify_img()
499 auth_method = &img_desc->img_auth_methods[i]; in auth_mod_verify_img()
[all …]
/rk3399_ARM-atf/lib/el3_runtime/aarch64/
H A Dcontext_debug.c87 for (unsigned int i = 0U; i < PLATFORM_CORE_COUNT; i++) { in report_allocated_memory() local
99 cpu_context_t *ctx = (cpu_context_t *)cm_get_context_by_index(i, in report_allocated_memory()
105 printf("| %9u | %8luB | %8luB ", i, gp_size, el3_size); in report_allocated_memory()
180 for (unsigned int i = 0U; i < CPU_CONTEXT_NUM; i++) { in report_ctx_memory_usage() local
181 const char *context_name = get_context_name_by_idx(i); in report_ctx_memory_usage()
185 total += report_allocated_memory(i); in report_ctx_memory_usage()
/rk3399_ARM-atf/plat/imx/imx8m/
H A Dimx_aipstz.c19 for (int i = 0; i < AIPSTZ_OPACR_NUM; i++) in imx_aipstz_init() local
20 mmio_write_32(aipstz->base + OPACR_OFFSET(i), aipstz->opacr[i]); in imx_aipstz_init()
/rk3399_ARM-atf/plat/imx/imx8m/include/
H A Dimx8m_csu.h63 #define CSU_CSLx(i, level, lk) \ argument
64 {CSU_CSL, .idx = (i), .csl_level = (level), .lock = (lk),}
66 #define CSU_HPx(i, val, lk) \ argument
67 {CSU_HP, .idx = (i), .hp = (val), .lock = (lk), }
69 #define CSU_SA(i, val, lk) \ argument
70 {CSU_SA, .idx = (i), .sa = (val), .lock = (lk), }
72 #define CSU_HPCTRL(i, val, lk) \ argument
73 {CSU_HPCONTROL, .idx = (i), .hpctrl = (val), .lock = (lk), }
/rk3399_ARM-atf/drivers/nxp/crypto/caam/src/
H A Dcaam.c239 int i = 0, ret = 0; in run_descriptor_jr() local
244 for (i = 0; i < desc_len; i++) { in run_descriptor_jr()
245 desc_word = desc_addr[i]; in run_descriptor_jr()
247 sec_out32((uint32_t *)&desc_addr[i], desc_word); in run_descriptor_jr()
291 int i = 0; in get_random() local
315 for (i = 0; i < bytes; i++) { in get_random()
318 rand_byte_swp[i] = 0; in get_random()
320 rand_byte_swp[i] = rand_byte[bytes - i - 1]; in get_random()
321 result = (result << 8) | rand_byte_swp[i]; in get_random()
/rk3399_ARM-atf/plat/intel/soc/common/soc/
H A Dsocfpga_handoff.c19 int i; in socfpga_get_handoff() local
37 for (i = 0; i < sizeof(handoff) / 4; i++) in socfpga_get_handoff()
38 buffer[i] = SWAP_UINT32(buffer[i]); in socfpga_get_handoff()
/rk3399_ARM-atf/plat/mediatek/mt8192/drivers/spm/
H A Dmt_spm_vcorefs.c320 uint32_t i; in dvfsrc_init() local
322 for (i = 0U; i < ARRAY_SIZE(dvfsrc_init_configs); i++) { in dvfsrc_init()
323 mmio_write_32(dvfsrc_init_configs[i].offset, in dvfsrc_init()
324 dvfsrc_init_configs[i].val); in dvfsrc_init()
340 uint32_t dvfs_v_mode, dvfsrc_rsrv, i; in spm_vcorefs_vcore_setting() local
352 for (i = 0; i < ARRAY_SIZE(opp_uv); i++) { in spm_vcorefs_vcore_setting()
355 opp_uv[i] = round_down((opp_uv[i] * VCORE_LV) / 100U, in spm_vcorefs_vcore_setting()
359 opp_uv[i] = round_up((opp_uv[i] * VCORE_HV) / 100U, in spm_vcorefs_vcore_setting()
362 spm_vcorefs_pwarp_cmd(i, __vcore_uv_to_pmic(opp_uv[i])); in spm_vcorefs_vcore_setting()
/rk3399_ARM-atf/docs/plat/
H A Dimx8ulp.rst1 NXP i.MX 8ULP
4 i.MX 8ULP is part of the ULP family with emphasis on extreme low-power techniques
5 using the 28 nm fully depleted silicon on insulator process. Like i.MX 7ULP,
6 i.MX 8ULP continues to be based on asymmetric architecture.
8 The i.MX 8ULP family of processors features NXP’s advanced implementation of the
20 `i.MX8ULP Applications Processors`_.
48 Target_SoC should be "imx8ulp" for i.MX8ULP SoC.
63 - i.MX Linux User's Guide
64 …`link <https://www.nxp.com/design/software/embedded-software/i-mx-software/embedded-linux-for-i-mx…
65 - i.MX Linux Reference Manual
[all …]
/rk3399_ARM-atf/tools/cert_create/src/
H A Dkey.c313 unsigned int i; in key_init() local
337 for (i = 0; i < num_keys; i++) { in key_init()
338 key = &keys[i]; in key_init()
355 unsigned int i; in key_get_by_opt() local
359 for (i = 0; i < num_keys; i++) { in key_get_by_opt()
360 key = &keys[i]; in key_get_by_opt()
371 unsigned int i; in key_cleanup() local
373 for (i = 0; i < num_keys; i++) { in key_cleanup()
374 EVP_PKEY_free(keys[i].key); in key_cleanup()
375 if (keys[i].fn != NULL) { in key_cleanup()
[all …]
/rk3399_ARM-atf/plat/intel/soc/common/drivers/ddr/
H A Dddr.c88 unsigned int i; in iossm_mb_read_response() local
100 for (i = 1; i < IOSSM_RESP_MAX_WORD_SIZE; i++) { in iossm_mb_read_response()
102 resp_data[i] = mmio_read_32(IO96B_CSR_REG(resp_param_reg)); in iossm_mb_read_response()
120 unsigned int i; in iossm_mb_send() local
139 for (i = 0; i < len; i++) { in iossm_mb_send()
141 IOSSM_MB_WRITE(IO96B_CSR_REG(cmd_param_reg), args[i]); in iossm_mb_send()
157 unsigned int i = 0; in ddr_iossm_mailbox_cmd() local
167 OPCODE_GET_MEM_INTF_INFO, payload, i); in ddr_iossm_mailbox_cmd()
172 OPCODE_GET_MEM_TECHNOLOGY, payload, i); in ddr_iossm_mailbox_cmd()
177 OPCODE_GET_MEM_WIDTH_INFO, payload, i); in ddr_iossm_mailbox_cmd()
[all …]
/rk3399_ARM-atf/plat/brcm/board/stingray/src/
H A Dbl2_setup.c370 uint32_t i, result; in board_detect_fru() local
380 for (i = EMMC_BOOT_PARTITION1; i <= EMMC_BOOT_PARTITION2; i++) { in board_detect_fru()
381 result = emmc_partition_select(i); in board_detect_fru()
383 ERROR("Switching to eMMC part %u failed\n", i); in board_detect_fru()
390 ERROR("Failed to read from eMMC part %u\n", i); in board_detect_fru()
400 WARN("FRU table not found in eMMC part %u\n", i); in board_detect_fru()
408 WARN("No FRU DDR info found in eMMC part %u\n", i); in board_detect_fru()
416 WARN("No FRU board info found in eMMC part %u\n", i); in board_detect_fru()
429 for (i = 0; i < BCM_MAX_NR_DDR; i++) { in board_detect_fru()
430 INFO("DDR channel index: %d\n", ddr_info.mcb[i].idx); in board_detect_fru()
[all …]
H A Dncsi.c23 unsigned int i = 0; in brcm_stingray_ncsi_init() local
48 for (i = 0; i < NITRO_NCSI_IOPAD_CONTROL_NUM; i++) { in brcm_stingray_ncsi_init()
49 mmio_clrsetbits_32((NITRO_NCSI_IOPAD_CONTROL_BASE + (i * 4)), in brcm_stingray_ncsi_init()
/rk3399_ARM-atf/plat/mediatek/drivers/booker/
H A Dbooker.c37 unsigned int i; in booker_flush() local
40 for (i = 0; i < ARRAY_SIZE(booker_mtsx_bases); i++) in booker_flush()
41 booker_mtsx_tc_flush(booker_mtsx_bases[i]); in booker_flush()
/rk3399_ARM-atf/plat/arm/board/neoverse_rd/platform/rdn2/
H A Drdn2_plat.c155 unsigned int i; in bl31_platform_setup() local
164 for (i = 0; i < ARRAY_SIZE(rdn2mc_dynamic_mmap); i++) { in bl31_platform_setup()
166 rdn2mc_dynamic_mmap[i].base_pa, in bl31_platform_setup()
167 rdn2mc_dynamic_mmap[i].base_va, in bl31_platform_setup()
168 rdn2mc_dynamic_mmap[i].size, in bl31_platform_setup()
169 rdn2mc_dynamic_mmap[i].attr); in bl31_platform_setup()
172 " i: %d " "(ret=%d)\n", i, ret); in bl31_platform_setup()
/rk3399_ARM-atf/plat/nxp/common/setup/
H A Dls_bl31_setup.c91 int i = 0; in bl31_early_platform_setup2() local
134 for (i = 0; i < dram_regions_info.num_dram_regions; in bl31_early_platform_setup2()
135 i++) { in bl31_early_platform_setup2()
136 dram_regions_info.region[i].addr = in bl31_early_platform_setup2()
137 loc_dram_regions_info->region[i].addr; in bl31_early_platform_setup2()
138 dram_regions_info.region[i].size = in bl31_early_platform_setup2()
139 loc_dram_regions_info->region[i].size; in bl31_early_platform_setup2()
140 VERBOSE("DRAM%d Size = %" PRIx64 "\n", i, in bl31_early_platform_setup2()
141 dram_regions_info.region[i].size); in bl31_early_platform_setup2()
/rk3399_ARM-atf/plat/qemu/qemu_sbsa/
H A Dsbsa_topology.c22 unsigned int i; in plat_get_power_domain_tree_desc() local
26 for (i = 0U; i < PLATFORM_CLUSTER_COUNT; i++) { in plat_get_power_domain_tree_desc()
27 power_domain_tree_desc[i + 1] = PLATFORM_MAX_CPUS_PER_CLUSTER; in plat_get_power_domain_tree_desc()
/rk3399_ARM-atf/plat/rockchip/rk3568/drivers/scmi/
H A Drk3568_clk.h11 #define CRU_CLKGATES_CON(i) (CRU_CLKGATE_CON0 + (i) * 4) argument
43 #define RK3568_PLLCON(i) (i * 0x4) argument
64 #define PMUCRU_CLKGATES_CON(i) (0x180 + (i) * 4) argument
/rk3399_ARM-atf/plat/arm/board/tc/
H A Dtc_sfcp.c56 for (uint8_t i = 1; i < ARRAY_SIZE(receiver_devices); i++) { in sfcp_platform_get_receive_link_id() local
57 if ((receiver_devices[i].type == device.type) && in sfcp_platform_get_receive_link_id()
58 (receiver_devices[i].device == device.device)) { in sfcp_platform_get_receive_link_id()
59 return i; in sfcp_platform_get_receive_link_id()

12345678910>>...25