Home
last modified time | relevance | path

Searched refs:i (Results 151 – 175 of 613) sorted by relevance

12345678910>>...25

/rk3399_ARM-atf/plat/st/stm32mp1/
H A Dstm32mp1_fconf_firewall.c57 uint8_t i; in stm32mp1_security_setup() local
70 for (i = 1U; i <= nb_regions; i++) { in stm32mp1_security_setup()
71 tzc400_update_filters(i, STM32MP1_FILTER_BIT_ALL); in stm32mp1_security_setup()
81 unsigned int i; in fconf_populate_stm32mp1_firewall() local
101 for (i = 0U; i < (unsigned int)(len / (sizeof(uint32_t) * STM32MP_REGION_PARAMS)); i++) { in fconf_populate_stm32mp1_firewall()
102 uint32_t idx = i * STM32MP_REGION_PARAMS; in fconf_populate_stm32mp1_firewall()
/rk3399_ARM-atf/drivers/nxp/crypto/caam/src/auth/
H A Dnxp_crypto.c81 int i = 0, ret = 0; in verify_hash() local
106 for (i = 0; i < SHA256_BYTES/4; i++) { in verify_hash()
107 VERBOSE("%x\n", *((uint32_t *)hash + i)); in verify_hash()
110 for (i = 0; i < digest_info_len; i++) { in verify_hash()
111 if (memcmp(hash, (hash_tbl + (i * digest_size)), in verify_hash()
/rk3399_ARM-atf/plat/brcm/board/stingray/src/
H A Dtz_sec.c135 int i; in plat_tz_master_default_cfg() local
138 for (i = 0; i < ARRAY_SIZE(tz_master_defaults); i++) { in plat_tz_master_default_cfg()
139 tz_master_set(tz_master_defaults[i].addr, in plat_tz_master_default_cfg()
140 tz_master_defaults[i].val, in plat_tz_master_default_cfg()
142 tz_master_set(tz_master_defaults[i].addr, in plat_tz_master_default_cfg()
143 ~tz_master_defaults[i].val, in plat_tz_master_default_cfg()
H A Dfsx.c182 unsigned int i, v, data; in fsx_init() local
333 for (i = 0; i < ae_count; i++) { in fsx_init()
334 VERBOSE(" - initialize AE%d\n", i); in fsx_init()
336 mmio_write_32(FSX_AEx_CONTROL_REGISTER(base, i), v); in fsx_init()
340 for (i = 0; i < dme_count; i++) { in fsx_init()
341 VERBOSE(" - initialize DME%d\n", i); in fsx_init()
349 mmio_write_32(FSX_DMEx_AXI_CONTROL(dme_base, i), v); in fsx_init()
351 mmio_read_32(FSX_DMEx_AXI_CONTROL(dme_base, i))); in fsx_init()
355 mmio_write_32(FSX_DMEx_WR_FIFO_THRESHOLD(dme_base, i), v); in fsx_init()
357 mmio_read_32(FSX_DMEx_WR_FIFO_THRESHOLD(dme_base, i))); in fsx_init()
[all …]
/rk3399_ARM-atf/plat/mediatek/drivers/emi_mpu/
H A Demi_mpu_common.c122 int region, i; in dump_emi_mpu_regions() local
130 for (i = 0; i < EMI_MPU_DGROUP_NUM; ++i) { in dump_emi_mpu_regions()
131 INFO("\tapc%d: 0x%x\n", i, mmio_read_32(EMI_MPU_APC(region, i))); in dump_emi_mpu_regions()
139 int i; in emi_mpu_set_protection() local
149 for (i = EMI_MPU_DGROUP_NUM - 1; i >= 0; i--) { in emi_mpu_set_protection()
150 end = (unsigned int)(region_info->end >> EMI_MPU_ALIGN_BITS) | (i << 24); in emi_mpu_set_protection()
152 if (_emi_mpu_set_protection(start, end, region_info->apc[i]) < 0) { in emi_mpu_set_protection()
154 start, end, region_info->apc[i]); in emi_mpu_set_protection()
/rk3399_ARM-atf/plat/arm/board/neoverse_rd/platform/rdv3/
H A Drdv3_bl31_setup.c162 for (int i = 1; i < ARRAY_SIZE(per_cpu_nodes_base); i++) { in bl31_plat_arch_setup() local
164 NRD_REMOTE_CHIP_MEM_OFFSET(i), in bl31_plat_arch_setup()
165 NRD_REMOTE_CHIP_MEM_OFFSET(i), in bl31_plat_arch_setup()
196 unsigned int i; in bl31_platform_setup() local
205 for (i = 0; i < ARRAY_SIZE(rdv3mc_dynamic_mmap); i++) { in bl31_platform_setup()
207 rdv3mc_dynamic_mmap[i].base_pa, in bl31_platform_setup()
208 rdv3mc_dynamic_mmap[i].base_va, in bl31_platform_setup()
209 rdv3mc_dynamic_mmap[i].size, in bl31_platform_setup()
210 rdv3mc_dynamic_mmap[i].attr); in bl31_platform_setup()
213 i, ret); in bl31_platform_setup()
/rk3399_ARM-atf/lib/libc/
H A Dsnprintf.c48 int i = 0; in unsigned_num_print() local
62 num_buf[i] = '0' + rem; in unsigned_num_print()
64 num_buf[i] = ascii_a + (rem - 10U); in unsigned_num_print()
66 i++; in unsigned_num_print()
70 width = i; in unsigned_num_print()
71 for (i = padn - width; i > 0; i--) { in unsigned_num_print()
74 for (i = width; i > 0; i--) { in unsigned_num_print()
75 CHECK_AND_PUT_CHAR(*s, n, *chars_printed, num_buf[i - 1]); in unsigned_num_print()
77 for (i = width + padn; i < 0; i++) { in unsigned_num_print()
/rk3399_ARM-atf/plat/mediatek/mt8183/
H A Dplat_debug.c23 unsigned int i; in circular_buffer_unlock() local
31 for (i = 1; i <= 4; ++i) in circular_buffer_unlock()
32 sync_writel(MP1_CPUTOP_PWR_CON + i * 4, in circular_buffer_unlock()
33 (mmio_read_32(MP1_CPUTOP_PWR_CON + i * 4) & ~(0x4))|(0x4)); in circular_buffer_unlock()
H A Dplat_pm.c308 unsigned int i; in plat_mtk_power_domain_on() local
315 for (i = 0; i < PLATFORM_MAX_CPUS_PER_CLUSTER; i++) { in plat_mtk_power_domain_on()
316 mcucfg_init_archstate(cluster, i, 1); in plat_mtk_power_domain_on()
317 mcucfg_set_bootaddr(cluster, i, secure_entrypoint); in plat_mtk_power_domain_on()
445 int i; in plat_mtk_validate_power_state() local
457 for (i = 0; !!mtk_pm_idle_states[i]; i++) { in plat_mtk_validate_power_state()
458 if (power_state == mtk_pm_idle_states[i]) in plat_mtk_validate_power_state()
463 if (!mtk_pm_idle_states[i]) in plat_mtk_validate_power_state()
466 i = 0; in plat_mtk_validate_power_state()
471 req_state->pwr_domain_state[i++] = state_id & in plat_mtk_validate_power_state()
[all …]
/rk3399_ARM-atf/plat/mediatek/drivers/spm/
H A Dmt_spm_rc_api_common.c131 uint32_t i; in mt_spm_dump_pmic_warp_reg() local
133 for (i = 0; i <= PMIC_WRAP_REG_1; i += PMIC_WRAP_REG_STEP) { in mt_spm_dump_pmic_warp_reg()
134 temp = mmio_read_32(PMIC_WRAP_BASE + i); in mt_spm_dump_pmic_warp_reg()
137 for (i = 0xC00; i <= PMIC_WRAP_REG_2; i += PMIC_WRAP_REG_STEP) { in mt_spm_dump_pmic_warp_reg()
138 temp = mmio_read_32(PMIC_WRAP_BASE + i); in mt_spm_dump_pmic_warp_reg()
141 for (i = 0xF00; i <= PMIC_WRAP_REG_3; i += PMIC_WRAP_REG_STEP) { in mt_spm_dump_pmic_warp_reg()
142 temp = mmio_read_32(PMIC_WRAP_BASE + i); in mt_spm_dump_pmic_warp_reg()
/rk3399_ARM-atf/plat/allwinner/common/
H A Dsunxi_security.c25 int i; in sunxi_security_setup() local
29 for (i = 0; i < SUNXI_SPC_NUM_PORTS; i++) in sunxi_security_setup()
30 mmio_write_32(SUNXI_SPC_DECPORT_SET_REG(i), 0xffffffff); in sunxi_security_setup()
/rk3399_ARM-atf/fdts/
H A Drd1ae.dts31 i-cache-size = <0x10000>;
32 i-cache-line-size = <0x40>;
33 i-cache-sets = <0x100>;
43 i-cache-size = <0x10000>;
44 i-cache-line-size = <0x40>;
45 i-cache-sets = <0x100>;
55 i-cache-size = <0x10000>;
56 i-cache-line-size = <0x40>;
57 i-cache-sets = <0x100>;
67 i-cache-size = <0x10000>;
[all …]
/rk3399_ARM-atf/tools/cert_create/src/
H A Dext.c56 unsigned int i; variable
78 for (i = 0; i < num_extensions; i++) {
79 ext = &extensions[i];
305 unsigned int i; in ext_get_by_opt() local
309 for (i = 0; i < num_extensions; i++) { in ext_get_by_opt()
310 ext = &extensions[i]; in ext_get_by_opt()
321 unsigned int i; in ext_cleanup() local
323 for (i = 0; i < num_extensions; i++) { in ext_cleanup()
324 if (extensions[i].arg != NULL) { in ext_cleanup()
325 void *ptr = (void *)extensions[i].arg; in ext_cleanup()
[all …]
/rk3399_ARM-atf/plat/socionext/uniphier/
H A Duniphier_scp.c49 int len, i; in uniphier_scp_send_packet() local
55 for (i = 0; i < len; i++) in uniphier_scp_send_packet()
56 word |= *packet++ << (8 * i); in uniphier_scp_send_packet()
75 int i; in uniphier_scp_send_cmd() local
80 for (i = 0; i < cmd_len; i++) { in uniphier_scp_send_cmd()
/rk3399_ARM-atf/plat/mediatek/drivers/apusys/mt8196/
H A Dapusys_security_ctrl_plat.c47 int i; in domain_remap_init() local
49 for (i = 0; i < ARRAY_SIZE(remap_domains); i++) { in domain_remap_init()
50 if (i < SEC_CTRL_REG_DOMAIN_NUM) in domain_remap_init()
51 lower_domain |= (remap_domains[i] << (i * REG_DOMAIN_BITS)); in domain_remap_init()
53 higher_domain |= (remap_domains[i] << in domain_remap_init()
54 ((i - SEC_CTRL_REG_DOMAIN_NUM) * REG_DOMAIN_BITS)); in domain_remap_init()
/rk3399_ARM-atf/plat/arm/board/corstone700/common/
H A Dcorstone700_topology.c19 int i; in plat_get_power_domain_tree_desc() local
28 for (i = 0; i < PLAT_ARM_CLUSTER_COUNT; i++) in plat_get_power_domain_tree_desc()
29 corstone700_power_domain_tree_desc[i + 2] = PLATFORM_CORE_COUNT; in plat_get_power_domain_tree_desc()
/rk3399_ARM-atf/plat/arm/board/corstone1000/common/
H A Dcorstone1000_topology.c19 int i; in plat_get_power_domain_tree_desc() local
28 for (i = 0; i < PLAT_ARM_CLUSTER_COUNT; i++) in plat_get_power_domain_tree_desc()
29 corstone1000_power_domain_tree_desc[i + 2] = PLATFORM_CORE_COUNT; in plat_get_power_domain_tree_desc()
/rk3399_ARM-atf/plat/imx/imx9/common/
H A Dimx9_bl31_setup.c85 for (unsigned int i = 0U; i < GPIO_NUM; i++) { in bl31_plat_arch_setup() local
86 mmio_write_32(gpio_base[i] + 0x10, 0xffffffff); in bl31_plat_arch_setup()
87 mmio_write_32(gpio_base[i] + 0x14, 0x3); in bl31_plat_arch_setup()
88 mmio_write_32(gpio_base[i] + 0x18, 0xffffffff); in bl31_plat_arch_setup()
89 mmio_write_32(gpio_base[i] + 0x1c, 0x3); in bl31_plat_arch_setup()
124 for (unsigned int i = 0U; i < PLATFORM_CORE_COUNT; i++) { in bl31_platform_setup() local
125 gicr_base = gicv3_driver_data->rdistif_base_addrs[i]; in bl31_platform_setup()
/rk3399_ARM-atf/plat/mediatek/drivers/gic600/
H A Dmt_gic_v3.c109 unsigned int i, proc_num; in mt_gic_rdistif_save() local
131 for (i = 0U; i < 8U; ++i) in mt_gic_rdistif_save()
132 gic_data.saved_prio[proc_num][i] = gicr_ipriorityr_read(gicr_base, i); in mt_gic_rdistif_save()
139 unsigned int i, proc_num; in mt_gic_rdistif_restore() local
152 for (i = 0U; i < 8U; ++i) in mt_gic_rdistif_restore()
153 gicr_ipriorityr_write(gicr_base, i, gic_data.saved_prio[proc_num][i]); in mt_gic_rdistif_restore()
166 unsigned int i, proc_num; in mt_gic_rdistif_restore_all() local
178 for (i = 0U; i < 8U; ++i) in mt_gic_rdistif_restore_all()
179 gicr_ipriorityr_write(gicr_base, i, gic_data.saved_prio[proc_num][i]); in mt_gic_rdistif_restore_all()
/rk3399_ARM-atf/drivers/renesas/common/ddr/ddr_a/
H A Dddr_init_e3.c37 uint32_t i, r2, r5, r6, r7, r12; in init_ddr() local
376 for (i = 0; i < 4; i++) { in init_ddr()
377 mmio_write_32(DBSC_DBPDRGA_0, 0xB1 + i * 0x20); in init_ddr()
379 mmio_write_32(DBSC_DBPDRGA_0, 0xB4 + i * 0x20); in init_ddr()
381 mmio_write_32(DBSC_DBPDRGA_0, 0xB3 + i * 0x20); in init_ddr()
385 mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); in init_ddr()
387 mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); in init_ddr()
389 mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); in init_ddr()
391 mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); in init_ddr()
394 mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); in init_ddr()
[all …]
/rk3399_ARM-atf/plat/rockchip/rk3399/drivers/pmu/
H A Dpmu.c913 int i; in suspend_apio() local
921 for (i = 0; i < 12; i++) { in suspend_apio()
922 iomux_status[i] = mmio_read_32(GRF_BASE + in suspend_apio()
923 GRF_GPIO2A_IOMUX + i * 4); in suspend_apio()
924 pull_mode_status[i] = mmio_read_32(GRF_BASE + in suspend_apio()
925 GRF_GPIO2A_P + i * 4); in suspend_apio()
1033 int i; in resume_apio() local
1040 for (i = 0; i < 12; i++) { in resume_apio()
1041 mmio_write_32(GRF_BASE + GRF_GPIO2A_P + i * 4, in resume_apio()
1042 REG_SOC_WMSK | pull_mode_status[i]); in resume_apio()
[all …]
/rk3399_ARM-atf/drivers/arm/gic/v3/
H A Dgicv3_main.c44 #define RESTORE_GICR_REG(base, ctx, name, i) \ argument
45 gicr_write_##name((base), (i), (ctx)->gicr_##name[(i)])
47 #define SAVE_GICR_REG(base, ctx, name, i) \ argument
48 (ctx)->gicr_##name[(i)] = gicr_read_##name((base), (i))
501 unsigned int i; in gicv3_its_save_disable() local
519 for (i = 0U; i < ARRAY_SIZE(its_ctx->gits_baser); i++) { in gicv3_its_save_disable()
520 its_ctx->gits_baser[i] = gits_read_baser(gits_base, i); in gicv3_its_save_disable()
535 unsigned int i; in gicv3_its_restore() local
549 for (i = 0U; i < ARRAY_SIZE(its_ctx->gits_baser); i++) { in gicv3_its_restore()
550 gits_write_baser(gits_base, i, its_ctx->gits_baser[i]); in gicv3_its_restore()
[all …]
/rk3399_ARM-atf/plat/rpi/common/
H A Drpi3_stack_protector.c19 size_t i; in plat_get_stack_protector_canary() local
25 for (i = 0U; i < ARRAY_SIZE(buf); i++) in plat_get_stack_protector_canary()
26 ret ^= buf[i]; in plat_get_stack_protector_canary()
/rk3399_ARM-atf/plat/qti/common/src/
H A Dqti_pm.c87 int i; in qti_validate_power_state() local
96 for (i = 0; !!qti_pm_idle_states[i]; i++) { in qti_validate_power_state()
99 qti_pm_idle_states[i]) in qti_validate_power_state()
101 if (power_state == qti_pm_idle_states[i]) in qti_validate_power_state()
107 if (!qti_pm_idle_states[i]) in qti_validate_power_state()
110 i = 0; in qti_validate_power_state()
114 for (i = QTI_PWR_LVL0; i <= PLAT_MAX_PWR_LVL; i++) { in qti_validate_power_state()
115 req_state->pwr_domain_state[i] = state_id & in qti_validate_power_state()
237 int i = 0; in qti_get_sys_suspend_power_state() local
251 req_state->pwr_domain_state[i++] = in qti_get_sys_suspend_power_state()
/rk3399_ARM-atf/docs/plat/
H A Dimx9.rst1 NXP i.MX 9 Series
4 Building on the market-proven i.MX 6 and i.MX 8 series, i.MX 9 series applications
8 (graphics, image, display, audio and voice). The i.MX 9 series, part of the EdgeVerse™
11 `i.MX9 Applications Processors`_.
39 Target_SoC should be "imx93" for i.MX93 SoC.
54 - i.MX Linux User's Guide
55 …`link <https://www.nxp.com/design/software/embedded-software/i-mx-software/embedded-linux-for-i-mx…
56 - i.MX Linux Reference Manual
57 …`link <https://www.nxp.com/design/software/embedded-software/i-mx-software/embedded-linux-for-i-mx…
59 ….com/products/processors-and-microcontrollers/arm-processors/i-mx-applications-processors/i-mx-9-p…

12345678910>>...25