1acb8b3caSAndre Przywara /* 2*49d98cd5SSamuel Holland * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved. 3acb8b3caSAndre Przywara * 4acb8b3caSAndre Przywara * SPDX-License-Identifier: BSD-3-Clause 5acb8b3caSAndre Przywara */ 6acb8b3caSAndre Przywara 709d40e0eSAntonio Nino Diaz #include <common/debug.h> 809d40e0eSAntonio Nino Diaz #include <lib/mmio.h> 909d40e0eSAntonio Nino Diaz 10978a8240SSamuel Holland #include <sunxi_ccu.h> 11acb8b3caSAndre Przywara #include <sunxi_mmap.h> 124ec1a239SAndre Przywara #include <sunxi_private.h> 13*49d98cd5SSamuel Holland #include <sunxi_spc.h> 14acb8b3caSAndre Przywara 15acb8b3caSAndre Przywara #define DMA_SEC_REG 0x20 16acb8b3caSAndre Przywara 17acb8b3caSAndre Przywara /* 18acb8b3caSAndre Przywara * Setup the peripherals to be accessible by non-secure world. 19acb8b3caSAndre Przywara * This will not work for the Secure Peripherals Controller (SPC) unless 20acb8b3caSAndre Przywara * a fuse it burnt (seems to be an erratum), but we do it nevertheless, 21acb8b3caSAndre Przywara * to allow booting on boards using secure boot. 22acb8b3caSAndre Przywara */ sunxi_security_setup(void)23acb8b3caSAndre Przywaravoid sunxi_security_setup(void) 24acb8b3caSAndre Przywara { 25acb8b3caSAndre Przywara int i; 26acb8b3caSAndre Przywara 27acb8b3caSAndre Przywara INFO("Configuring SPC Controller\n"); 28acb8b3caSAndre Przywara /* SPC setup: set all devices to non-secure */ 29*49d98cd5SSamuel Holland for (i = 0; i < SUNXI_SPC_NUM_PORTS; i++) 30*49d98cd5SSamuel Holland mmio_write_32(SUNXI_SPC_DECPORT_SET_REG(i), 0xffffffff); 31acb8b3caSAndre Przywara 32acb8b3caSAndre Przywara /* set MBUS clocks, bus clocks (AXI/AHB/APB) and PLLs to non-secure */ 33acb8b3caSAndre Przywara mmio_write_32(SUNXI_CCU_SEC_SWITCH_REG, 0x7); 34acb8b3caSAndre Przywara 35506ffe50SSamuel Holland /* Set R_PRCM bus clocks to non-secure */ 36978a8240SSamuel Holland mmio_write_32(SUNXI_R_PRCM_SEC_SWITCH_REG, 0x1); 37acb8b3caSAndre Przywara 38acb8b3caSAndre Przywara /* Set all DMA channels (16 max.) to non-secure */ 39acb8b3caSAndre Przywara mmio_write_32(SUNXI_DMA_BASE + DMA_SEC_REG, 0xffff); 40acb8b3caSAndre Przywara } 41