913 	int i;  in suspend_apio()  local
921 	for (i = 0; i < 12; i++) {  in suspend_apio()
922 		iomux_status[i] = mmio_read_32(GRF_BASE +  in suspend_apio()
923 				GRF_GPIO2A_IOMUX + i * 4);  in suspend_apio()
924 		pull_mode_status[i] = mmio_read_32(GRF_BASE +  in suspend_apio()
925 				GRF_GPIO2A_P + i * 4);  in suspend_apio()
1033 	int i;  in resume_apio()  local
1040 	for (i = 0; i < 12; i++) {  in resume_apio()
1041 		mmio_write_32(GRF_BASE + GRF_GPIO2A_P + i * 4,  in resume_apio()
1042 			      REG_SOC_WMSK | pull_mode_status[i]);  in resume_apio()
1043 		mmio_write_32(GRF_BASE + GRF_GPIO2A_IOMUX + i * 4,  in resume_apio()
1044 			      REG_SOC_WMSK | iomux_status[i]);  in resume_apio()
1062 	int i;  in suspend_gpio()  local
1066 	for (i = 0; i < count; i++) {  in suspend_gpio()
1067 		gpio_set_value(suspend_gpio[i].index, suspend_gpio[i].polarity);  in suspend_gpio()
1068 		gpio_set_direction(suspend_gpio[i].index, GPIO_DIR_OUT);  in suspend_gpio()
1077 	int i;  in resume_gpio()  local
1081 	for (i = count - 1; i >= 0; i--) {  in resume_gpio()
1082 		gpio_set_value(suspend_gpio[i].index,  in resume_gpio()
1083 			       !suspend_gpio[i].polarity);  in resume_gpio()
1084 		gpio_set_direction(suspend_gpio[i].index, GPIO_DIR_OUT);  in resume_gpio()
1238 	int i;  in grf_register_save()  local
1247 	for (i = 0; i < 4; i++)  in grf_register_save()
1248 		store_grf_ddrc_con[i] =  in grf_register_save()
1249 			mmio_read_32(GRF_BASE + GRF_DDRC0_CON0 + i * 4);  in grf_register_save()
1256 	int i;  in grf_register_restore()  local
1271 	for (i = 0; i < 4; i++)  in grf_register_restore()
1272 		mmio_write_32(GRF_BASE + GRF_DDRC0_CON0 + i * 4,  in grf_register_restore()
1273 			      REG_SOC_WMSK | store_grf_ddrc_con[i]);  in grf_register_restore()
1280 	int i;  in cru_register_save()  local
1282 	for (i = 0; i <= CRU_SDIO0_CON1; i = i + 4)  in cru_register_save()
1283 		store_cru[i / 4] = mmio_read_32(CRU_BASE + i);  in cru_register_save()
1288 	int i;  in cru_register_restore()  local
1290 	for (i = 0; i <= CRU_SDIO0_CON1; i = i + 4) {  in cru_register_restore()
1296 		if ((i == CRU_CLKSEL_CON6) ||  in cru_register_restore()
1297 		    (i >= CRU_PLL_CON(ABPLL_ID, 0) &&  in cru_register_restore()
1298 		     i <= CRU_PLL_CON(DPLL_ID, 5)))  in cru_register_restore()
1301 		if ((i == CRU_PLL_CON(ALPLL_ID, 2)) ||  in cru_register_restore()
1302 		    (i == CRU_PLL_CON(CPLL_ID, 2)) ||  in cru_register_restore()
1303 		    (i == CRU_PLL_CON(GPLL_ID, 2)) ||  in cru_register_restore()
1304 		    (i == CRU_PLL_CON(NPLL_ID, 2)) ||  in cru_register_restore()
1305 		    (i == CRU_PLL_CON(VPLL_ID, 2)))  in cru_register_restore()
1306 			mmio_write_32(CRU_BASE + i, store_cru[i / 4]);  in cru_register_restore()
1311 		else if ((i > 0x27c && i < 0x2b0) || (i == 0x508))  in cru_register_restore()
1312 			mmio_write_32(CRU_BASE + i, store_cru[i / 4]);  in cru_register_restore()
1314 			mmio_write_32(CRU_BASE + i,  in cru_register_restore()
1315 				      REG_SOC_WMSK | store_cru[i / 4]);  in cru_register_restore()
1321 	int i;  in wdt_register_save()  local
1323 	for (i = 0; i < 2; i++) {  in wdt_register_save()
1324 		store_wdt0[i] = mmio_read_32(WDT0_BASE + i * 4);  in wdt_register_save()
1325 		store_wdt1[i] = mmio_read_32(WDT1_BASE + i * 4);  in wdt_register_save()
1332 	int i;  in wdt_register_restore()  local
1334 	for (i = 1; i >= 0; i--) {  in wdt_register_restore()
1335 		mmio_write_32(WDT0_BASE + i * 4, store_wdt0[i]);  in wdt_register_restore()
1336 		mmio_write_32(WDT1_BASE + i * 4, store_wdt1[i]);  in wdt_register_restore()