Searched hist:e1b76cb06a70b5c3d9b46a71c26e7e889dcee91b (Results 1 – 5 of 5) sorted by relevance
| /rk3399_ARM-atf/include/lib/cpus/aarch64/ |
| H A D | cortex_a520.h | e1b76cb06a70b5c3d9b46a71c26e7e889dcee91b Tue Jul 23 14:41:34 UTC 2024 Jagdish Gediya <jagdish.gediya@arm.com> feat(tc): enable Last-level cache (LLC)
The EXTLLC bit in CPUECTLR_EL1 register indicates that an external
Last-level cache is present in the system.
This bit is not set for CPUs on TC3 platform despite there is
presence of LLC in MCN, so set them.
Change-Id: I5f889e67dce2b1d00e4ee66a8c255cf7911825b0
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>
|
| H A D | cortex_x925.h | e1b76cb06a70b5c3d9b46a71c26e7e889dcee91b Tue Jul 23 14:41:34 UTC 2024 Jagdish Gediya <jagdish.gediya@arm.com> feat(tc): enable Last-level cache (LLC)
The EXTLLC bit in CPUECTLR_EL1 register indicates that an external
Last-level cache is present in the system.
This bit is not set for CPUs on TC3 platform despite there is
presence of LLC in MCN, so set them.
Change-Id: I5f889e67dce2b1d00e4ee66a8c255cf7911825b0
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>
|
| H A D | cortex_a725.h | e1b76cb06a70b5c3d9b46a71c26e7e889dcee91b Tue Jul 23 14:41:34 UTC 2024 Jagdish Gediya <jagdish.gediya@arm.com> feat(tc): enable Last-level cache (LLC)
The EXTLLC bit in CPUECTLR_EL1 register indicates that an external
Last-level cache is present in the system.
This bit is not set for CPUs on TC3 platform despite there is
presence of LLC in MCN, so set them.
Change-Id: I5f889e67dce2b1d00e4ee66a8c255cf7911825b0
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>
|
| /rk3399_ARM-atf/plat/arm/board/tc/include/ |
| H A D | tc_helpers.S | e1b76cb06a70b5c3d9b46a71c26e7e889dcee91b Tue Jul 23 14:41:34 UTC 2024 Jagdish Gediya <jagdish.gediya@arm.com> feat(tc): enable Last-level cache (LLC)
The EXTLLC bit in CPUECTLR_EL1 register indicates that an external
Last-level cache is present in the system.
This bit is not set for CPUs on TC3 platform despite there is
presence of LLC in MCN, so set them.
Change-Id: I5f889e67dce2b1d00e4ee66a8c255cf7911825b0
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>
|
| H A D | platform_def.h | e1b76cb06a70b5c3d9b46a71c26e7e889dcee91b Tue Jul 23 14:41:34 UTC 2024 Jagdish Gediya <jagdish.gediya@arm.com> feat(tc): enable Last-level cache (LLC)
The EXTLLC bit in CPUECTLR_EL1 register indicates that an external
Last-level cache is present in the system.
This bit is not set for CPUs on TC3 platform despite there is
presence of LLC in MCN, so set them.
Change-Id: I5f889e67dce2b1d00e4ee66a8c255cf7911825b0
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>
|