1 /* 2 * Copyright (c) 2021-2024, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef CORTEX_A520_H 8 #define CORTEX_A520_H 9 10 #define CORTEX_A520_MIDR U(0x410FD800) 11 12 /******************************************************************************* 13 * CPU Extended Control register specific definitions 14 ******************************************************************************/ 15 #define CORTEX_A520_CPUACTLR_EL1 S3_0_C15_C1_0 16 17 #define CORTEX_A520_CPUECTLR_EL1 S3_0_C15_C1_4 18 #define CORTEX_A520_CPUECTLR_EL1_EXTLLC_BIT U(0) 19 20 /******************************************************************************* 21 * CPU Auxiliary Control register 1 specific definitions. 22 ******************************************************************************/ 23 #define CORTEX_A520_CPUACTLR_EL1 S3_0_C15_C1_0 24 25 /******************************************************************************* 26 * CPU Power Control register specific definitions 27 ******************************************************************************/ 28 #define CORTEX_A520_CPUPWRCTLR_EL1 S3_0_C15_C2_7 29 #define CORTEX_A520_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1) 30 31 #ifndef __ASSEMBLER__ 32 #if ERRATA_A520_2938996 33 long check_erratum_cortex_a520_2938996(long cpu_rev); 34 #else check_erratum_cortex_a520_2938996(long cpu_rev)35static inline long check_erratum_cortex_a520_2938996(long cpu_rev) 36 { 37 return 0; 38 } 39 #endif /* ERRATA_A520_2938996 */ 40 #endif /* __ASSEMBLER__ */ 41 42 #endif /* CORTEX_A520_H */ 43