| #
553b70c3 |
| 19-Aug-2024 |
Manish V Badarkhe <manish.badarkhe@arm.com> |
Merge changes from topic "ar/asymmetricSupport" into integration
* changes:
feat(tc): enable trbe errata flags for Cortex-A520 and X4
feat(cm): asymmetric feature support for trbe
refactor(err
Merge changes from topic "ar/asymmetricSupport" into integration
* changes:
feat(tc): enable trbe errata flags for Cortex-A520 and X4
feat(cm): asymmetric feature support for trbe
refactor(errata-abi): move EXTRACT_PARTNUM to arch.h
feat(cpus): workaround for Cortex-A520(2938996) and Cortex-X4(2726228)
feat(tc): make SPE feature asymmetric
feat(cm): handle asymmetry for SPE feature
feat(cm): support for asymmetric feature among cores
feat(cpufeat): add new feature state for asymmetric features
show more ...
|
| #
4a97ff51 |
| 05-Aug-2024 |
Arvind Ram Prakash <arvind.ramprakash@arm.com> |
feat(cpus): workaround for Cortex-A520(2938996) and Cortex-X4(2726228)
This patch implements errata functions for two errata, both of them
disable TRBE as a workaround. This patch doesn't have funct
feat(cpus): workaround for Cortex-A520(2938996) and Cortex-X4(2726228)
This patch implements errata functions for two errata, both of them
disable TRBE as a workaround. This patch doesn't have functions
that disable TRBE but only implemented helper functions that are
used to detect cores affected by Errata 2938996(Cortex-A520) & 2726228(Cortex-X4)
Cortex-X4 SDEN documentation:
https://developer.arm.com/documentation/SDEN2432808/latest
Cortex-A520 SDEN Documentation:
https://developer.arm.com/documentation/SDEN-2444153/latest
Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I8f886a1c21698f546a0996c719cc27dc0a23633a
show more ...
|
| #
80da8264 |
| 24-Jul-2024 |
Manish V Badarkhe <manish.badarkhe@arm.com> |
Merge changes from topic "us_dsu_pmu" into integration
* changes:
feat(tc): enable Last-level cache (LLC)
feat(cpus): add sysreg_bitfield_insert_from_gpr macro
feat(tc): add DSU PMU node for t
Merge changes from topic "us_dsu_pmu" into integration
* changes:
feat(tc): enable Last-level cache (LLC)
feat(cpus): add sysreg_bitfield_insert_from_gpr macro
feat(tc): add DSU PMU node for tc3
feat(tc): enable el1 access to DSU PMU registers
style(tc): remove comment for plat_reset_handler
fix(context-mgmt): keep actlr_el2 value in the init context
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|
| #
e1b76cb0 |
| 23-Jul-2024 |
Jagdish Gediya <jagdish.gediya@arm.com> |
feat(tc): enable Last-level cache (LLC)
The EXTLLC bit in CPUECTLR_EL1 register indicates that an external
Last-level cache is present in the system.
This bit is not set for CPUs on TC3 platform de
feat(tc): enable Last-level cache (LLC)
The EXTLLC bit in CPUECTLR_EL1 register indicates that an external
Last-level cache is present in the system.
This bit is not set for CPUs on TC3 platform despite there is
presence of LLC in MCN, so set them.
Change-Id: I5f889e67dce2b1d00e4ee66a8c255cf7911825b0
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>
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|
| #
7b78a022 |
| 19-Dec-2023 |
Bipin Ravi <bipin.ravi@arm.com> |
Merge "fix(cpus): workaround for Cortex-A520 erratum 2858100" into integration
|
| #
34db3531 |
| 09-Dec-2023 |
Arvind Ram Prakash <arvind.ramprakash@arm.com> |
fix(cpus): workaround for Cortex-A520 erratum 2858100
Cortex-A520 erratum 2858100 is a Cat B erratum that applies to
all revisions <=r0p1 and is still open. The workaround is to
set bit[29] of CPUAC
fix(cpus): workaround for Cortex-A520 erratum 2858100
Cortex-A520 erratum 2858100 is a Cat B erratum that applies to
all revisions <=r0p1 and is still open. The workaround is to
set bit[29] of CPUACTLR_EL1.
SDEN Documentation:
https://developer.arm.com/documentation/SDEN-2444153/latest
Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I5a07163f919352583b03328abd5659bf7b268677
show more ...
|
| #
62d1adb6 |
| 13-Dec-2023 |
Bipin Ravi <bipin.ravi@arm.com> |
Merge changes from topic "sm/erratum" into integration
* changes:
fix(cpus): workaround for Cortex-A520 erratum 2630792
fix(cpus): workaround for Cortex-X2 erratum 2778471
fix(cpus): workaroun
Merge changes from topic "sm/erratum" into integration
* changes:
fix(cpus): workaround for Cortex-A520 erratum 2630792
fix(cpus): workaround for Cortex-X2 erratum 2778471
fix(cpus): workaround for Cortex-A710 erratum 2778471
show more ...
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| #
f03bfc30 |
| 10-Dec-2023 |
Sona Mathew <sonarebecca.mathew@arm.com> |
fix(cpus): workaround for Cortex-A520 erratum 2630792
Cortex-A520 erratum is a Cat B erratum that applies
to revisions r0p0 and r0p1 and is still open.
The workaround is to set CPUACTLR_EL1[38] to 1
fix(cpus): workaround for Cortex-A520 erratum 2630792
Cortex-A520 erratum is a Cat B erratum that applies
to revisions r0p0 and r0p1 and is still open.
The workaround is to set CPUACTLR_EL1[38] to 1.
SDEN Documentation:
https://developer.arm.com/documentation/SDEN-2444153/latest
Change-Id: Idb6f32f680ee1378a57c2d2f809ea847fffe5910
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>
show more ...
|
| #
e87102f3 |
| 29-Jun-2023 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge changes from topic "gr/cpu_rename" into integration
* changes:
chore: rename hayes to a520
chore: rename hunter to a720
chore: rename hunter_elp to cortex-x4
|
| #
dea3d71e |
| 28-Jun-2023 |
Govindraj Raja <govindraj.raja@arm.com> |
chore: rename hayes to a520
Rename Cortex-hayes to Cortes-A520
Change-Id: Ic574b55b1aaf11b5bf7b583e244245e7b54bdb22
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
|