1dea3d71eSGovindraj Raja /* 2e1b76cb0SJagdish Gediya * Copyright (c) 2021-2024, Arm Limited. All rights reserved. 3dea3d71eSGovindraj Raja * 4dea3d71eSGovindraj Raja * SPDX-License-Identifier: BSD-3-Clause 5dea3d71eSGovindraj Raja */ 6dea3d71eSGovindraj Raja 7dea3d71eSGovindraj Raja #ifndef CORTEX_A520_H 8dea3d71eSGovindraj Raja #define CORTEX_A520_H 9dea3d71eSGovindraj Raja 10dea3d71eSGovindraj Raja #define CORTEX_A520_MIDR U(0x410FD800) 11dea3d71eSGovindraj Raja 12dea3d71eSGovindraj Raja /******************************************************************************* 13dea3d71eSGovindraj Raja * CPU Extended Control register specific definitions 14dea3d71eSGovindraj Raja ******************************************************************************/ 1534db3531SArvind Ram Prakash #define CORTEX_A520_CPUACTLR_EL1 S3_0_C15_C1_0 1634db3531SArvind Ram Prakash 17dea3d71eSGovindraj Raja #define CORTEX_A520_CPUECTLR_EL1 S3_0_C15_C1_4 18e1b76cb0SJagdish Gediya #define CORTEX_A520_CPUECTLR_EL1_EXTLLC_BIT U(0) 19dea3d71eSGovindraj Raja 20dea3d71eSGovindraj Raja /******************************************************************************* 21f03bfc30SSona Mathew * CPU Auxiliary Control register 1 specific definitions. 22f03bfc30SSona Mathew ******************************************************************************/ 23f03bfc30SSona Mathew #define CORTEX_A520_CPUACTLR_EL1 S3_0_C15_C1_0 24f03bfc30SSona Mathew 25f03bfc30SSona Mathew /******************************************************************************* 26dea3d71eSGovindraj Raja * CPU Power Control register specific definitions 27dea3d71eSGovindraj Raja ******************************************************************************/ 28dea3d71eSGovindraj Raja #define CORTEX_A520_CPUPWRCTLR_EL1 S3_0_C15_C2_7 29dea3d71eSGovindraj Raja #define CORTEX_A520_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1) 30dea3d71eSGovindraj Raja 31*4a97ff51SArvind Ram Prakash #ifndef __ASSEMBLER__ 32*4a97ff51SArvind Ram Prakash #if ERRATA_A520_2938996 33*4a97ff51SArvind Ram Prakash long check_erratum_cortex_a520_2938996(long cpu_rev); 34*4a97ff51SArvind Ram Prakash #else check_erratum_cortex_a520_2938996(long cpu_rev)35*4a97ff51SArvind Ram Prakashstatic inline long check_erratum_cortex_a520_2938996(long cpu_rev) 36*4a97ff51SArvind Ram Prakash { 37*4a97ff51SArvind Ram Prakash return 0; 38*4a97ff51SArvind Ram Prakash } 39*4a97ff51SArvind Ram Prakash #endif /* ERRATA_A520_2938996 */ 40*4a97ff51SArvind Ram Prakash #endif /* __ASSEMBLER__ */ 41*4a97ff51SArvind Ram Prakash 42dea3d71eSGovindraj Raja #endif /* CORTEX_A520_H */ 43