Searched hist:de7781158923a9c87debc5a89ce4fabfd0fc93bc (Results 1 – 6 of 6) sorted by relevance
| /rk3399_rockchip-uboot/arch/arm/mach-socfpga/include/mach/ |
| H A D | clock_manager_gen5.h | de7781158923a9c87debc5a89ce4fabfd0fc93bc Tue Apr 25 18:44:33 UTC 2017 Ley Foon Tan <ley.foon.tan@intel.com> arm: socfpga: Restructure clock manager driver
Restructure clock manager driver in the preparation to support A10.
Move the Gen5 specific code to _gen5 files.
- Change all uint32_t to u32 and change to use macro BIT(n) for bit shift.
- Check return value from wait_for_bit(). So change return type to int for
cm_write_with_phase() and cm_basic_init().
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
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| H A D | clock_manager.h | de7781158923a9c87debc5a89ce4fabfd0fc93bc Tue Apr 25 18:44:33 UTC 2017 Ley Foon Tan <ley.foon.tan@intel.com> arm: socfpga: Restructure clock manager driver
Restructure clock manager driver in the preparation to support A10.
Move the Gen5 specific code to _gen5 files.
- Change all uint32_t to u32 and change to use macro BIT(n) for bit shift.
- Check return value from wait_for_bit(). So change return type to int for
cm_write_with_phase() and cm_basic_init().
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
| /rk3399_rockchip-uboot/arch/arm/mach-socfpga/ |
| H A D | clock_manager_gen5.c | de7781158923a9c87debc5a89ce4fabfd0fc93bc Tue Apr 25 18:44:33 UTC 2017 Ley Foon Tan <ley.foon.tan@intel.com> arm: socfpga: Restructure clock manager driver
Restructure clock manager driver in the preparation to support A10.
Move the Gen5 specific code to _gen5 files.
- Change all uint32_t to u32 and change to use macro BIT(n) for bit shift.
- Check return value from wait_for_bit(). So change return type to int for
cm_write_with_phase() and cm_basic_init().
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
| H A D | clock_manager.c | de7781158923a9c87debc5a89ce4fabfd0fc93bc Tue Apr 25 18:44:33 UTC 2017 Ley Foon Tan <ley.foon.tan@intel.com> arm: socfpga: Restructure clock manager driver
Restructure clock manager driver in the preparation to support A10.
Move the Gen5 specific code to _gen5 files.
- Change all uint32_t to u32 and change to use macro BIT(n) for bit shift.
- Check return value from wait_for_bit(). So change return type to int for
cm_write_with_phase() and cm_basic_init().
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
| H A D | Makefile | de7781158923a9c87debc5a89ce4fabfd0fc93bc Tue Apr 25 18:44:33 UTC 2017 Ley Foon Tan <ley.foon.tan@intel.com> arm: socfpga: Restructure clock manager driver
Restructure clock manager driver in the preparation to support A10.
Move the Gen5 specific code to _gen5 files.
- Change all uint32_t to u32 and change to use macro BIT(n) for bit shift.
- Check return value from wait_for_bit(). So change return type to int for
cm_write_with_phase() and cm_basic_init().
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
|
| H A D | spl.c | de7781158923a9c87debc5a89ce4fabfd0fc93bc Tue Apr 25 18:44:33 UTC 2017 Ley Foon Tan <ley.foon.tan@intel.com> arm: socfpga: Restructure clock manager driver
Restructure clock manager driver in the preparation to support A10.
Move the Gen5 specific code to _gen5 files.
- Change all uint32_t to u32 and change to use macro BIT(n) for bit shift.
- Check return value from wait_for_bit(). So change return type to int for
cm_write_with_phase() and cm_basic_init().
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
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