| #
19d1f1a2 |
| 29-Jul-2017 |
Tom Rini <trini@konsulko.com> |
Merge git://git.denx.de/u-boot-socfpga
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| #
6867e19a |
| 26-Jul-2017 |
Tien Fong Chee <tien.fong.chee@intel.com> |
arm: socfpga: Restructure FPGA driver in the preparation to support A10
Move FPGA driver which is Gen5 specific code into Gen5 driver file and keeping common FPGA driver intact. All the changes are
arm: socfpga: Restructure FPGA driver in the preparation to support A10
Move FPGA driver which is Gen5 specific code into Gen5 driver file and keeping common FPGA driver intact. All the changes are still keeping in driver/fpga/ and no functional change. Subsequent patch would move FPGA manager driver from arch/arm into driver/fpga/.
Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Dinh Nguyen <dinguyen@kernel.org>
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| #
753a4dde |
| 18-May-2017 |
Tom Rini <trini@konsulko.com> |
Merge branch 'master' of git://git.denx.de/u-boot-socfpga
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| #
d89e979c |
| 25-Apr-2017 |
Ley Foon Tan <ley.foon.tan@intel.com> |
arm: socfpga: Enable build for Arria 10
Update Kconfig and Makefile to enable Arria 10. Clean up Makefile and sorting *.o alphanumerically.
Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
arm: socfpga: Enable build for Arria 10
Update Kconfig and Makefile to enable Arria 10. Clean up Makefile and sorting *.o alphanumerically.
Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
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| #
35b9800f |
| 25-Apr-2017 |
Ley Foon Tan <ley.foon.tan@intel.com> |
arm: socfpga: Add misc support for Arria 10
Add misc support for Arria 10.
Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
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| #
caf36e1e |
| 25-Apr-2017 |
Ley Foon Tan <ley.foon.tan@intel.com> |
arm: socfpga: Add pinmux for Arria 10
Add pinmux support for Arria 10.
Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
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| #
177ba1f9 |
| 25-Apr-2017 |
Ley Foon Tan <ley.foon.tan@intel.com> |
arm: socfpga: Add clock driver for Arria 10
Add clock driver support for Arria 10.
Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
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| #
827e6a7e |
| 25-Apr-2017 |
Ley Foon Tan <ley.foon.tan@intel.com> |
arm: socfpga: Add reset driver support for Arria 10
Add reset driver support for Arria 10.
Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.c
arm: socfpga: Add reset driver support for Arria 10
Add reset driver support for Arria 10.
Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
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| #
d1c559af |
| 25-Apr-2017 |
Ley Foon Tan <ley.foon.tan@intel.com> |
arm: socfpga: Restructure misc driver
Restructure misc driver in the preparation to support A10. Move the Gen5 specific code to gen5 file.
Change all uint32_t_to u32.
Signed-off-by: Ley Foon Tan <
arm: socfpga: Restructure misc driver
Restructure misc driver in the preparation to support A10. Move the Gen5 specific code to gen5 file.
Change all uint32_t_to u32.
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
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| #
4ddd541d |
| 25-Apr-2017 |
Ley Foon Tan <ley.foon.tan@intel.com> |
arm: socfpga: Restructure system manager
Restructure system manager in the preparation to support A10. No functional change.
Change uint32_t to u32.
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel
arm: socfpga: Restructure system manager
Restructure system manager in the preparation to support A10. No functional change.
Change uint32_t to u32.
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
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| #
2b09ea48 |
| 25-Apr-2017 |
Ley Foon Tan <ley.foon.tan@intel.com> |
arm: socfpga: Restructure reset manager driver
Restructure reset manager driver in the preparation to support A10. Move the Gen5 specific code to gen5 files.
Signed-off-by: Ley Foon Tan <ley.foon.t
arm: socfpga: Restructure reset manager driver
Restructure reset manager driver in the preparation to support A10. Move the Gen5 specific code to gen5 files.
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
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| #
de778115 |
| 25-Apr-2017 |
Ley Foon Tan <ley.foon.tan@intel.com> |
arm: socfpga: Restructure clock manager driver
Restructure clock manager driver in the preparation to support A10. Move the Gen5 specific code to _gen5 files.
- Change all uint32_t to u32 and chang
arm: socfpga: Restructure clock manager driver
Restructure clock manager driver in the preparation to support A10. Move the Gen5 specific code to _gen5 files.
- Change all uint32_t to u32 and change to use macro BIT(n) for bit shift. - Check return value from wait_for_bit(). So change return type to int for cm_write_with_phase() and cm_basic_init().
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
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| #
34059d8f |
| 20-Dec-2015 |
Tom Rini <trini@konsulko.com> |
Merge branch 'master' of git://www.denx.de/git/u-boot-socfpga
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| #
e5ad7d98 |
| 02-Dec-2015 |
Dinh Nguyen <dinguyen@opensource.altera.com> |
arm: socfpga: remove building scan manager
The scan manager is not needed for the Arria10. Edit the makefile to build the scan manager for arria5 and cyclone5 only.
Signed-off-by: Dinh Nguyen <ding
arm: socfpga: remove building scan manager
The scan manager is not needed for the Arria10. Edit the makefile to build the scan manager for arria5 and cyclone5 only.
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com> Acked-by: Marek Vasut <marex@denx.de>
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| #
8e535af2 |
| 05-Dec-2015 |
Marek Vasut <marex@denx.de> |
arm: socfpga: Introduce common board code
The SoCFPGA has reached a point where every single board code become the same, since each and every single board is probed equally from OF. Move the common
arm: socfpga: Introduce common board code
The SoCFPGA has reached a point where every single board code become the same, since each and every single board is probed equally from OF. Move the common board code into arch/arm/mach-socfpga/ .
Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
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| #
c851a245 |
| 24-Aug-2015 |
Tom Rini <trini@konsulko.com> |
Merge git://git.denx.de/u-boot-socfpga
Conflicts: configs/socfpga_arria5_defconfig configs/socfpga_cyclone5_defconfig configs/socfpga_socrates_defconfig
Merged these by hand and re-ran savedefco
Merge git://git.denx.de/u-boot-socfpga
Conflicts: configs/socfpga_arria5_defconfig configs/socfpga_cyclone5_defconfig configs/socfpga_socrates_defconfig
Merged these by hand and re-ran savedefconfig on them.
Signed-off-by: Tom Rini <trini@konsulko.com>
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| #
ca62d2e1 |
| 02-Aug-2015 |
Marek Vasut <marex@denx.de> |
arm: socfpga: Move wrappers into platform directory
Move the wrappers for QTS-generated files into platform directory out of the board directory. The trick here is to add -I to CFLAGS such that it p
arm: socfpga: Move wrappers into platform directory
Move the wrappers for QTS-generated files into platform directory out of the board directory. The trick here is to add -I to CFLAGS such that it points to the board directory in source tree and thus the qts/ directory there is still reachable.
Signed-off-by: Marek Vasut <marex@denx.de>
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| #
bd48c061 |
| 01-Aug-2015 |
Dinh Nguyen <dinguyen@opensource.altera.com> |
arm: socfpga: misc: Add support for printing FPGA type
Add code which uses the new functions for obtaining FPGA ID from the scan manager. This new code prints the FPGA model attached to the SoCFPGA
arm: socfpga: misc: Add support for printing FPGA type
Add code which uses the new functions for obtaining FPGA ID from the scan manager. This new code prints the FPGA model attached to the SoCFPGA during boot and sets environment variable "fpgatype", which can be used to determine the FPGA model in U-Boot scripts.
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com> Signed-off-by: Marek Vasut <marex@denx.de>
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| #
05a21721 |
| 21-Apr-2015 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
ARM: socfpga: move SoC sources to mach-socfpga
Our recent trend is to collect SoC files into arch/arm/mach-(SOC).
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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