UPSTREAM: wait_bit: use wait_for_bit_le32 and remove wait_for_bit

wait_for_bit callers use the 32 bit LE version

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Daniel Schwie

UPSTREAM: wait_bit: use wait_for_bit_le32 and remove wait_for_bit

wait_for_bit callers use the 32 bit LE version

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Change-Id: I638846de7db29711fb7c778cc8304b507de057fe
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 48263504c8d501678acaa90c075f3f7cda17c316)
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>

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Merge branch 'master' of git://git.denx.de/u-boot-socfpga

arm: socfpga: Add clock driver for Arria 10

Add clock driver support for Arria 10.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>

arm: socfpga: Restructure clock manager driver

Restructure clock manager driver in the preparation to support A10.
Move the Gen5 specific code to _gen5 files.

- Change all uint32_t to u32 and chang

arm: socfpga: Restructure clock manager driver

Restructure clock manager driver in the preparation to support A10.
Move the Gen5 specific code to _gen5 files.

- Change all uint32_t to u32 and change to use macro BIT(n) for bit shift.
- Check return value from wait_for_bit(). So change return type to int for
cm_write_with_phase() and cm_basic_init().

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>

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Merge branch 'master' of git://git.denx.de/u-boot-socfpga

arm: socfpga: set the mpuclk divider in the Altera group register

The mpuclk register in the Altera group of the clock manager
divides the mpu_clk that is generated from the C0 output of the main
pl

arm: socfpga: set the mpuclk divider in the Altera group register

The mpuclk register in the Altera group of the clock manager
divides the mpu_clk that is generated from the C0 output of the main
pll.

Without this patch, the default value of the register is 1, so the mpuclk
will always get divided by 2 if the correct value is not set. For example,
on the Arria5 socdk board, the MPU clock is only 525 MHz, and it should be
1.05 GHz.

Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>

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Merge git://git.denx.de/u-boot-socfpga

Conflicts:
configs/socfpga_arria5_defconfig
configs/socfpga_cyclone5_defconfig
configs/socfpga_socrates_defconfig

Merged these by hand and re-ran savedefco

Merge git://git.denx.de/u-boot-socfpga

Conflicts:
configs/socfpga_arria5_defconfig
configs/socfpga_cyclone5_defconfig
configs/socfpga_socrates_defconfig

Merged these by hand and re-ran savedefconfig on them.

Signed-off-by: Tom Rini <trini@konsulko.com>

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arm: socfpga: Fix delay in clock manager

This code claims it needs to wait 7us, yet it uses get_timer() function
which operates with millisecond granularity. Use timer_get_us() instead,
which operat

arm: socfpga: Fix delay in clock manager

This code claims it needs to wait 7us, yet it uses get_timer() function
which operates with millisecond granularity. Use timer_get_us() instead,
which operates with microsecond granularity.

Signed-off-by: Marek Vasut <marex@denx.de>

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arm: socfpga: clock: Clean up pll_config.h

Extract the clock configuration horribleness caused by pll_config.h in
the following manner.

First of all, introduce a few new accessors which return valu

arm: socfpga: clock: Clean up pll_config.h

Extract the clock configuration horribleness caused by pll_config.h in
the following manner.

First of all, introduce a few new accessors which return values of
various clocks used in clock_manager.c and use them in clock_manager.c .
These accessors replace those few macros which came from pll_config.h
originally. Also introduce an accessor which returns the struct cm_config
default configuration for the clock manager used in SPL.

The accessors are implemented in a board-specific wrap_pll_config.c
file, whose sole purpose is to include the qts-generated pll_config.h
and provide only the necessary values to the clock manager.

The purpose of this design is to limit the scope of inclusion for the
pll_config.h , which thus far was included build-wide and poluted the
namespace. With this change, the inclusion is limited to just the new
wrap_pll_config.c file, which in turn provides three simple functions
for the clock_manager.c to use.

Signed-off-by: Marek Vasut <marex@denx.de>

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arm: socfpga: clock: Get rid of cm_config_t typedef

Get rid of this cryptic typedef and replace it with explicit struct cm_config.

Signed-off-by: Marek Vasut <marex@denx.de>

ARM: socfpga: move SoC sources to mach-socfpga

Our recent trend is to collect SoC files into arch/arm/mach-(SOC).

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>