Searched hist:c63e137014cf148bc1d234128941dccee3d519ae (Results 1 – 8 of 8) sorted by relevance
| /rk3399_rockchip-uboot/board/freescale/p1_twr/ |
| H A D | ddr.c | c63e137014cf148bc1d234128941dccee3d519ae Tue Jun 25 18:37:48 UTC 2013 York Sun <yorksun@freescale.com> powerpc/mpc8xxx: Add memory reset control
JEDEC spec requires the clocks to be stable before deasserting reset
signal for RDIMMs. Clocks start when any chip select is enabled and
clock control register is set. This patch also adds the interface to
toggle memory reset signal if needed by the boards.
Signed-off-by: York Sun <yorksun@freescale.com>
|
| /rk3399_rockchip-uboot/board/freescale/bsc9132qds/ |
| H A D | ddr.c | c63e137014cf148bc1d234128941dccee3d519ae Tue Jun 25 18:37:48 UTC 2013 York Sun <yorksun@freescale.com> powerpc/mpc8xxx: Add memory reset control
JEDEC spec requires the clocks to be stable before deasserting reset
signal for RDIMMs. Clocks start when any chip select is enabled and
clock control register is set. This patch also adds the interface to
toggle memory reset signal if needed by the boards.
Signed-off-by: York Sun <yorksun@freescale.com>
|
| /rk3399_rockchip-uboot/board/freescale/bsc9131rdb/ |
| H A D | ddr.c | c63e137014cf148bc1d234128941dccee3d519ae Tue Jun 25 18:37:48 UTC 2013 York Sun <yorksun@freescale.com> powerpc/mpc8xxx: Add memory reset control
JEDEC spec requires the clocks to be stable before deasserting reset
signal for RDIMMs. Clocks start when any chip select is enabled and
clock control register is set. This patch also adds the interface to
toggle memory reset signal if needed by the boards.
Signed-off-by: York Sun <yorksun@freescale.com>
|
| /rk3399_rockchip-uboot/board/freescale/common/ |
| H A D | qixis.c | c63e137014cf148bc1d234128941dccee3d519ae Tue Jun 25 18:37:48 UTC 2013 York Sun <yorksun@freescale.com> powerpc/mpc8xxx: Add memory reset control
JEDEC spec requires the clocks to be stable before deasserting reset
signal for RDIMMs. Clocks start when any chip select is enabled and
clock control register is set. This patch also adds the interface to
toggle memory reset signal if needed by the boards.
Signed-off-by: York Sun <yorksun@freescale.com>
|
| /rk3399_rockchip-uboot/board/freescale/p1010rdb/ |
| H A D | ddr.c | c63e137014cf148bc1d234128941dccee3d519ae Tue Jun 25 18:37:48 UTC 2013 York Sun <yorksun@freescale.com> powerpc/mpc8xxx: Add memory reset control
JEDEC spec requires the clocks to be stable before deasserting reset
signal for RDIMMs. Clocks start when any chip select is enabled and
clock control register is set. This patch also adds the interface to
toggle memory reset signal if needed by the boards.
Signed-off-by: York Sun <yorksun@freescale.com>
|
| /rk3399_rockchip-uboot/board/freescale/p1_p2_rdb_pc/ |
| H A D | ddr.c | c63e137014cf148bc1d234128941dccee3d519ae Tue Jun 25 18:37:48 UTC 2013 York Sun <yorksun@freescale.com> powerpc/mpc8xxx: Add memory reset control
JEDEC spec requires the clocks to be stable before deasserting reset
signal for RDIMMs. Clocks start when any chip select is enabled and
clock control register is set. This patch also adds the interface to
toggle memory reset signal if needed by the boards.
Signed-off-by: York Sun <yorksun@freescale.com>
|
| /rk3399_rockchip-uboot/board/freescale/corenet_ds/ |
| H A D | ddr.c | c63e137014cf148bc1d234128941dccee3d519ae Tue Jun 25 18:37:48 UTC 2013 York Sun <yorksun@freescale.com> powerpc/mpc8xxx: Add memory reset control
JEDEC spec requires the clocks to be stable before deasserting reset
signal for RDIMMs. Clocks start when any chip select is enabled and
clock control register is set. This patch also adds the interface to
toggle memory reset signal if needed by the boards.
Signed-off-by: York Sun <yorksun@freescale.com>
|
| /rk3399_rockchip-uboot/include/configs/ |
| H A D | T4240QDS.h | c63e137014cf148bc1d234128941dccee3d519ae Tue Jun 25 18:37:48 UTC 2013 York Sun <yorksun@freescale.com> powerpc/mpc8xxx: Add memory reset control
JEDEC spec requires the clocks to be stable before deasserting reset
signal for RDIMMs. Clocks start when any chip select is enabled and
clock control register is set. This patch also adds the interface to
toggle memory reset signal if needed by the boards.
Signed-off-by: York Sun <yorksun@freescale.com>
|