Searched hist:"8177 e1ef0c9f275cf5abc73d47216b02f501f089" (Results 1 – 5 of 5) sorted by relevance
| /rk3399_ARM-atf/lib/cpus/aarch64/ |
| H A D | cortex_a65.S | 8177e1ef0c9f275cf5abc73d47216b02f501f089 Wed Nov 05 18:38:21 UTC 2025 Xialin Liu <xialin.liu@arm.com> fix(cpus): workaround for Cortex-A65 erratum 1541130
Cortex-A65 erratum 1541130 is a Cat B erratum that applies
to r0p0, r1p0, r1p1, r1p2 revisions of the CPU and is still open.
This erratum can be avoided by disable stage1 page table walk for
lower Els (EL1 and EL0) in EL3, so 'AT' speculative fetch at any
point produces either the correct result or failure without TLB
allocation.
SDEN documentation:
https://developer.arm.com/documentation/SDEN1065159/latest/
Change-Id: I72498f60f8449193ed4b5b2a9e7a08530e786ec3
Signed-off-by: Xialin Liu <xialin.liu@arm.com>
|
| /rk3399_ARM-atf/docs/getting_started/ |
| H A D | build-options.rst | 8177e1ef0c9f275cf5abc73d47216b02f501f089 Wed Nov 05 18:38:21 UTC 2025 Xialin Liu <xialin.liu@arm.com> fix(cpus): workaround for Cortex-A65 erratum 1541130
Cortex-A65 erratum 1541130 is a Cat B erratum that applies
to r0p0, r1p0, r1p1, r1p2 revisions of the CPU and is still open.
This erratum can be avoided by disable stage1 page table walk for
lower Els (EL1 and EL0) in EL3, so 'AT' speculative fetch at any
point produces either the correct result or failure without TLB
allocation.
SDEN documentation:
https://developer.arm.com/documentation/SDEN1065159/latest/
Change-Id: I72498f60f8449193ed4b5b2a9e7a08530e786ec3
Signed-off-by: Xialin Liu <xialin.liu@arm.com>
|
| /rk3399_ARM-atf/docs/design/ |
| H A D | cpu-specific-build-macros.rst | 8177e1ef0c9f275cf5abc73d47216b02f501f089 Wed Nov 05 18:38:21 UTC 2025 Xialin Liu <xialin.liu@arm.com> fix(cpus): workaround for Cortex-A65 erratum 1541130
Cortex-A65 erratum 1541130 is a Cat B erratum that applies
to r0p0, r1p0, r1p1, r1p2 revisions of the CPU and is still open.
This erratum can be avoided by disable stage1 page table walk for
lower Els (EL1 and EL0) in EL3, so 'AT' speculative fetch at any
point produces either the correct result or failure without TLB
allocation.
SDEN documentation:
https://developer.arm.com/documentation/SDEN1065159/latest/
Change-Id: I72498f60f8449193ed4b5b2a9e7a08530e786ec3
Signed-off-by: Xialin Liu <xialin.liu@arm.com>
|
| /rk3399_ARM-atf/lib/cpus/ |
| H A D | cpu-ops.mk | 8177e1ef0c9f275cf5abc73d47216b02f501f089 Wed Nov 05 18:38:21 UTC 2025 Xialin Liu <xialin.liu@arm.com> fix(cpus): workaround for Cortex-A65 erratum 1541130
Cortex-A65 erratum 1541130 is a Cat B erratum that applies
to r0p0, r1p0, r1p1, r1p2 revisions of the CPU and is still open.
This erratum can be avoided by disable stage1 page table walk for
lower Els (EL1 and EL0) in EL3, so 'AT' speculative fetch at any
point produces either the correct result or failure without TLB
allocation.
SDEN documentation:
https://developer.arm.com/documentation/SDEN1065159/latest/
Change-Id: I72498f60f8449193ed4b5b2a9e7a08530e786ec3
Signed-off-by: Xialin Liu <xialin.liu@arm.com>
|
| /rk3399_ARM-atf/ |
| H A D | Makefile | 8177e1ef0c9f275cf5abc73d47216b02f501f089 Wed Nov 05 18:38:21 UTC 2025 Xialin Liu <xialin.liu@arm.com> fix(cpus): workaround for Cortex-A65 erratum 1541130
Cortex-A65 erratum 1541130 is a Cat B erratum that applies
to r0p0, r1p0, r1p1, r1p2 revisions of the CPU and is still open.
This erratum can be avoided by disable stage1 page table walk for
lower Els (EL1 and EL0) in EL3, so 'AT' speculative fetch at any
point produces either the correct result or failure without TLB
allocation.
SDEN documentation:
https://developer.arm.com/documentation/SDEN1065159/latest/
Change-Id: I72498f60f8449193ed4b5b2a9e7a08530e786ec3
Signed-off-by: Xialin Liu <xialin.liu@arm.com>
|