16ad216dcSImre Kis/* 252e89e9eSBoyan Karatotev * Copyright (c) 2019-2025, Arm Limited. All rights reserved. 36ad216dcSImre Kis * 46ad216dcSImre Kis * SPDX-License-Identifier: BSD-3-Clause 56ad216dcSImre Kis */ 66ad216dcSImre Kis#include <arch.h> 76ad216dcSImre Kis 86ad216dcSImre Kis#include <asm_macros.S> 96ad216dcSImre Kis#include <common/bl_common.h> 106ad216dcSImre Kis#include <common/debug.h> 116ad216dcSImre Kis#include <cortex_a65.h> 126ad216dcSImre Kis#include <cpu_macros.S> 13b62673c6SBoyan Karatotev#include <dsu_macros.S> 146ad216dcSImre Kis#include <plat_macros.S> 156ad216dcSImre Kis 166ad216dcSImre Kis/* Hardware handled coherency */ 176ad216dcSImre Kis#if !HW_ASSISTED_COHERENCY 186ad216dcSImre Kis#error "Cortex-A65 must be compiled with HW_ASSISTED_COHERENCY enabled" 196ad216dcSImre Kis#endif 206ad216dcSImre Kis 216ad216dcSImre Kis/* 64-bit only core */ 226ad216dcSImre Kis#if CTX_INCLUDE_AARCH32_REGS 236ad216dcSImre Kis#error "Cortex-A65 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 246ad216dcSImre Kis#endif 256ad216dcSImre Kis 2689dba82dSBoyan Karatotevcpu_reset_prologue cortex_a65 2789dba82dSBoyan Karatotev 28b62673c6SBoyan Karatotevworkaround_reset_start cortex_a65, ERRATUM(936184), ERRATA_DSU_936184 29b62673c6SBoyan Karatotev errata_dsu_936184_wa_impl 30b62673c6SBoyan Karatotevworkaround_reset_end cortex_a65, ERRATUM(936184) 31b62673c6SBoyan Karatotev 32b62673c6SBoyan Karatotevcheck_erratum_custom_start cortex_a65, ERRATUM(936184) 33b62673c6SBoyan Karatotev check_errata_dsu_936184_impl 34b62673c6SBoyan Karatotev ret 35b62673c6SBoyan Karatotevcheck_erratum_custom_end cortex_a65, ERRATUM(936184) 366ad216dcSImre Kis 37015e1cd5SXialin Liuworkaround_reset_start cortex_a65, ERRATUM(1179935), ERRATA_A65_1179935 38015e1cd5SXialin Liu sysreg_bit_set CORTEX_A65_CPUACTLR_EL1, BIT(49) 39015e1cd5SXialin Liuworkaround_reset_end cortex_a65, ERRATUM(1179935) 40015e1cd5SXialin Liu 41015e1cd5SXialin Liucheck_erratum_ls cortex_a65, ERRATUM(1179935), CPU_REV(0, 0) 42015e1cd5SXialin Liu 43ede3a236SXialin Liuworkaround_reset_start cortex_a65, ERRATUM(1227419), ERRATA_A65_1227419 44ede3a236SXialin Liu sysreg_bit_set CORTEX_A65_CPUACTLR_EL1, BIT(51) 45ede3a236SXialin Liuworkaround_reset_end cortex_a65, ERRATUM(1227419) 46ede3a236SXialin Liu 47ede3a236SXialin Liucheck_erratum_ls cortex_a65, ERRATUM(1227419), CPU_REV(1, 0) 48ede3a236SXialin Liu 49*8177e1efSXialin Liu/* Due to the nature of the errata it is applied unconditionally when chosen */ 50*8177e1efSXialin Liucheck_erratum_chosen cortex_a65, ERRATUM(1541130), ERRATA_A65_1541130 51*8177e1efSXialin Liu/* erratum workaround is interleaved with generic code */ 52*8177e1efSXialin Liuadd_erratum_entry cortex_a65, ERRATUM(1541130), ERRATA_A65_1541130 53*8177e1efSXialin Liu 5452e89e9eSBoyan Karatotevcpu_reset_func_start cortex_a65 5552e89e9eSBoyan Karatotevcpu_reset_func_end cortex_a65 566ad216dcSImre Kis 576ad216dcSImre Kisfunc cortex_a65_cpu_pwr_dwn 586ad216dcSImre Kis mrs x0, CORTEX_A65_CPUPWRCTLR_EL1 596ad216dcSImre Kis orr x0, x0, #CORTEX_A65_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 606ad216dcSImre Kis msr CORTEX_A65_CPUPWRCTLR_EL1, x0 616ad216dcSImre Kis isb 626ad216dcSImre Kis ret 636ad216dcSImre Kisendfunc cortex_a65_cpu_pwr_dwn 646ad216dcSImre Kis 656ad216dcSImre Kis.section .rodata.cortex_a65_regs, "aS" 666ad216dcSImre Kiscortex_a65_regs: /* The ascii list of register names to be reported */ 676ad216dcSImre Kis .asciz "cpuectlr_el1", "" 686ad216dcSImre Kis 696ad216dcSImre Kisfunc cortex_a65_cpu_reg_dump 706ad216dcSImre Kis adr x6, cortex_a65_regs 716ad216dcSImre Kis mrs x8, CORTEX_A65_ECTLR_EL1 726ad216dcSImre Kis ret 736ad216dcSImre Kisendfunc cortex_a65_cpu_reg_dump 746ad216dcSImre Kis 756ad216dcSImre Kisdeclare_cpu_ops cortex_a65, CORTEX_A65_MIDR, \ 766ad216dcSImre Kis cortex_a65_reset_func, \ 776ad216dcSImre Kis cortex_a65_cpu_pwr_dwn 78