Merge changes from topic "ssbs_errata_catchup" into integration

* changes:
fix(cpus): workaround for Neoverse-N3 erratum 3456111
fix(cpus): workaround for Neoverse-N2 erratum 3324339
fix(cpus)

Merge changes from topic "ssbs_errata_catchup" into integration

* changes:
fix(cpus): workaround for Neoverse-N3 erratum 3456111
fix(cpus): workaround for Neoverse-N2 erratum 3324339
fix(cpus): workaround for Neoverse-N1 erratum 3324349

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Merge "fix(cpus): workaround for Neoverse-V2 erratum 3442699" into integration

fix(cpus): workaround for Neoverse-N3 erratum 3456111

Neoverse-N3 erratum 3456111 is a Cat B erratum that applies
to revisions r0p0 and r0p1 and is still open.

This errata can be avoided by adding

fix(cpus): workaround for Neoverse-N3 erratum 3456111

Neoverse-N3 erratum 3456111 is a Cat B erratum that applies
to revisions r0p0 and r0p1 and is still open.

This errata can be avoided by adding a speculation barrier
instruction following writes to the SSBS register to
ensure the new value of PSTATE.SSBS affects the subsequent
instructions in the execution stream under speculation.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-3050973

Change-Id: I1685c2cacbe64ddf70501e8cce94b4fbf03f0ba0
Signed-off-by: John Powell <john.powell@arm.com>

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Merge "fix(cpus): workaround for C1-Pro erratum 3619847" into integration

Merge changes from topic "xl/c1pro-errata" into integration

* changes:
fix(cpus): workaround for C1-Pro erratum 3686597
fix(cpus): workaround for C1-Pro erratum 3300099
fix(cpus): workaround f

Merge changes from topic "xl/c1pro-errata" into integration

* changes:
fix(cpus): workaround for C1-Pro erratum 3686597
fix(cpus): workaround for C1-Pro erratum 3300099
fix(cpus): workaround for C1-Pro erratum 3338470
fix(cpus): workaround for C1-Pro erratum 3362007
fix(cpus): workaround for C1-Pro erratum 3684268
fix(cpus): workaround for C1-Pro erratum 3694158
fix(cpus): workaround for C1-Pro erratum 3706576

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fix(cpus): workaround for Neoverse-N2 erratum 3324339

Neoverse-N2 erratum 3324339 is a Cat B erratum that applies
to revisions r0p0, r0p1, r0p2 and r0p3 and is still open.

This errata can be avoide

fix(cpus): workaround for Neoverse-N2 erratum 3324339

Neoverse-N2 erratum 3324339 is a Cat B erratum that applies
to revisions r0p0, r0p1, r0p2 and r0p3 and is still open.

This errata can be avoided by adding a speculation barrier
instruction following writes to the SSBS register to
ensure the new value of PSTATE.SSBS affects the subsequent
instructions in the execution stream under speculation.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-1982442

Change-Id: I6b023279816005cfa459bc6947f60b1a3c0f2380
Signed-off-by: John Powell <john.powell@arm.com>

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fix(cpus): workaround for Neoverse-N1 erratum 3324349

Neoverse-N1 erratum 3324349 is a Cat B erratum that applies
to all revisions <= r4p1, and is still open.

This errata can be avoided by adding a

fix(cpus): workaround for Neoverse-N1 erratum 3324349

Neoverse-N1 erratum 3324349 is a Cat B erratum that applies
to all revisions <= r4p1, and is still open.

This errata can be avoided by adding a speculation barrier
instruction following writes to the SSBS register to
ensure the new value of PSTATE.SSBS affects the subsequent
instructions in the execution stream under speculation.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-885747

Change-Id: I1f142027ed73135d78c368be926072c2f73eab46
Signed-off-by: John Powell <john.powell@arm.com>

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fix(cpus): workaround for Neoverse-V2 erratum 3442699

Neoverse-V2 erratum 3442699 applies to r0p0, r0p1, and r0p2
and it is still open.

PE may execute incorrect instructions when icache is enabled.

fix(cpus): workaround for Neoverse-V2 erratum 3442699

Neoverse-V2 erratum 3442699 applies to r0p0, r0p1, and r0p2
and it is still open.

PE may execute incorrect instructions when icache is enabled.
As workaround, Set CPUACTLR_EL1[36] before enabling icache.

SDEN: https://developer.arm.com/documentation/SDEN-2332927/latest

Change-Id: I38edc6ba445223091c3933cbca35b56db491c926
Signed-off-by: Jaiprakash Singh <jaiprakashs@marvell.com>
Signed-off-by: Chandrakala Chavva <cchavva@cavium.com>
Reviewed-by: Chandrakala Chavva <cchavva@marvell.com>
Tested-by: Chandrakala Chavva <cchavva@marvell.com>

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fix(cpus): workaround for C1-Pro erratum 3619847

C1-Pro erratum 3619847 is a Cat B erratum that applies to
CPU revision r0p0 and is fixed in r1p0.

This erratum can be avoided by setting CPUACTLR2_E

fix(cpus): workaround for C1-Pro erratum 3619847

C1-Pro erratum 3619847 is a Cat B erratum that applies to
CPU revision r0p0 and is fixed in r1p0.

This erratum can be avoided by setting CPUACTLR2_EL1[42] to 1.
Only a minor performance drop is expected when mixing SME and
non-SME store instructions.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-3273080/1300/?lang=en

Change-Id: Id92e7180df20d973e4e2d112c4f187a561a4d924
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpus): workaround for C1-Pro erratum 3686597

C1-Pro erratum 3686597 is a Cat B erratum that applies
to revisions r0p0, r1p0 and is fixed in r1p1.

This erratum can be avoided by setting IMP_CPUE

fix(cpus): workaround for C1-Pro erratum 3686597

C1-Pro erratum 3686597 is a Cat B erratum that applies
to revisions r0p0, r1p0 and is fixed in r1p1.

This erratum can be avoided by setting IMP_CPUECTLR_EL1[57]
to 1.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-3273080/1300/?lang=en

Change-Id: I59a5d9316bf66793eae5dac08102231d0e2640fb
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpus): workaround for C1-Pro erratum 3300099

C1-Pro erratum 3300099 is a Cat B erratum that applies
to revisions r0p0, r1p0, and is fixed in r1p1.

This is workaround for accessing ICH_VMCR_EL2.

fix(cpus): workaround for C1-Pro erratum 3300099

C1-Pro erratum 3300099 is a Cat B erratum that applies
to revisions r0p0, r1p0, and is fixed in r1p1.

This is workaround for accessing ICH_VMCR_EL2.
When ICH_VMCR_EL2.VBPR1 is written in Secure state (SCR_EL3.NS==0)
and then subsequently read in Non-secure state (SCR_EL3.NS==1), a
wrong value might be returned. The same issue exists in the opposite way.

Adding workaround in EL3 software that performs context save/restore
on a change of Security state to use a value of SCR_EL3.NS when
accessing ICH_VMCR_EL2 that reflects the Security state that owns the
data being saved or restored. For example, EL3 software should set
SCR_EL3.NS to 1 when saving or restoring the value ICH_VMCR_EL2 for
Non-secure(or Realm) state. EL3 software should clear
SCR_EL3.NS to 0 when saving or restoring the value ICH_VMCR_EL2 for
Secure state.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-3273080/1300/?lang=en

Change-Id: If24d3230c4b4e87fcb831d446cf0d0c68c95ea18
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpus): workaround for C1-Pro erratum 3338470

C1-Pro erratum 3338470 is a Cat B erratum that applies
to revision r0p0, and is fixed in r1p0.

This errata can be avoid by having a speculation barr

fix(cpus): workaround for C1-Pro erratum 3338470

C1-Pro erratum 3338470 is a Cat B erratum that applies
to revision r0p0, and is fixed in r1p0.

This errata can be avoid by having a speculation barrier
instruction following writes to the SSBS register to
ensure the new value of PSTATE.SSBS affects the subsequent
instructions in the execution stream under speculation.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-3273080/1300/?lang=en

Change-Id: I86e2b8f70ceb468c75c0386a790641d51eeea9cb
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpus): workaround for C1-Pro erratum 3362007

C1-Pro erratum 3362007 is a Cat B erratum that applies to
CPU revision r0p0 and is fixed in r1p0.

This erratum can be avoided by setting CPUACTLR2_E

fix(cpus): workaround for C1-Pro erratum 3362007

C1-Pro erratum 3362007 is a Cat B erratum that applies to
CPU revision r0p0 and is fixed in r1p0.

This erratum can be avoided by setting CPUACTLR2_EL1[27] to 1.
Only a minor increase in power consumption is expected.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-3273080/1300/?lang=en

Change-Id: I529e9812bddffe927c986f9b5ee135f4866aa455
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpus): workaround for C1-Pro erratum 3684268

C1-Pro erratum 3684268 is a Cat B erratum that applies
to revisions r0p0, r1p0 and it is fixed in r1p1.

The erratum is avoided by disabling the affe

fix(cpus): workaround for C1-Pro erratum 3684268

C1-Pro erratum 3684268 is a Cat B erratum that applies
to revisions r0p0, r1p0 and it is fixed in r1p1.

The erratum is avoided by disabling the affected prefetcher,
which is done by setting CPUECTLR2_EL1[49] to 1.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-3273080/1300/?lang=en

Change-Id: I7929e931572471370b1a899d412b11f1c4d206c8
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpus): workaround for C1-Pro erratum 3694158

C1-Pro erratum 3694158 is a Cat B erratum that applies
to revisions r0p0, r1p0 and r1p1, it is fixed in r1p2.

This erratum can be avoided by inserti

fix(cpus): workaround for C1-Pro erratum 3694158

C1-Pro erratum 3694158 is a Cat B erratum that applies
to revisions r0p0, r1p0 and r1p1, it is fixed in r1p2.

This erratum can be avoided by inserting a DMB LD after
each DSB ST instruction with a CPU implementation specific
patch sequence.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-3273080/1300/?lang=en

Change-Id: I38f0fb6565110c579ab16b76e0f4ca601fa1b912
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpus): workaround for C1-Pro erratum 3706576

C1-Pro erratum 3706576 is a Cat B erratum that applies to
CPU revisions r0p0 and r1p0, and is fixed in r1p1.

This erratum might cause data corruptio

fix(cpus): workaround for C1-Pro erratum 3706576

C1-Pro erratum 3706576 is a Cat B erratum that applies to
CPU revisions r0p0 and r1p0, and is fixed in r1p1.

This erratum might cause data corruption when Memory read
effect crossing a 64B boundary, which can be avoided by
setting CPUACTLR2_EL1[37] to 1. Setting this bit is expected
to have a negligible performance impact.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-3273080/1300/?lang=en

Change-Id: Ie427e56c682065bdf82da9b11e71da6383db4e73
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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Merge changes from topic "ssbs_errata_catchup" into integration

* changes:
fix(cpus): workaround for Cortex-A720AE erratum 3456103
fix(cpus): workaround for Cortex-A720 erratum 3456091
fix(cpu

Merge changes from topic "ssbs_errata_catchup" into integration

* changes:
fix(cpus): workaround for Cortex-A720AE erratum 3456103
fix(cpus): workaround for Cortex-A720 erratum 3456091
fix(cpus): workaround for Cortex-A715 erratum 3456084
fix(cpus): workaround for Cortex-X2 erratum 3324338
fix(cpus): workaround for Cortex-A710 erratum 3324338

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Merge changes from topic "xl/c1premium-errata" into integration

* changes:
fix(cpus): workaround for C1-Premium erratum 3324333
fix(cpus): workaround for C1-Premium erratum 4102704
fix(cpus):

Merge changes from topic "xl/c1premium-errata" into integration

* changes:
fix(cpus): workaround for C1-Premium erratum 3324333
fix(cpus): workaround for C1-Premium erratum 4102704
fix(cpus): workaround for C1-Premium erratum 3926381
fix(cpus): workaround for C1-Premium erratum 3865171
fix(cpus): workaround for C1-Premium erratum 3815514
fix(cpus): workaround for C1-Premium erratum 3705939
fix(cpus): workaround for C1-Premium erratum 3684152
fix(cpus): workaround for C1-Premium erratum 3651221
fix(cpus): workaround for C1-Premium erratum 3502731

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fix(cpus): workaround for C1-Premium erratum 3324333

C1-Premium erratum 3324333 is a Cat B erratum that applies
to revision r0p0, and it is fixed in r1p0.

This errata can be avoided by having a spe

fix(cpus): workaround for C1-Premium erratum 3324333

C1-Premium erratum 3324333 is a Cat B erratum that applies
to revision r0p0, and it is fixed in r1p0.

This errata can be avoided by having a speculation barrier instruction
to ensure the new value of PSTATE.SSBS affects the subsequent
instructions in the execution stream under speculation.

SDEN documentation:
https://developer.arm.com/documentation/111078/latest

Change-Id: Ic9f09c56e7cc94f3d45e86d284971ee2b4b0fb40
Signed-off-by: Xialin Liu <xialin.liu@arm.com>
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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fix(cpus): workaround for C1-Premium erratum 4102704

C1-Premium erratum 4102704 is a Cat B erratum that applies
to revisions r0p0, r1p0 and it is still open.

The erratum can be avoided by setting C

fix(cpus): workaround for C1-Premium erratum 4102704

C1-Premium erratum 4102704 is a Cat B erratum that applies
to revisions r0p0, r1p0 and it is still open.

The erratum can be avoided by setting CPUACTLR4_EL1[23] to 1.
Overall expected performance degradation is ~1.36%, but
isolated benchmark components might see higher or lower impact.

SDEN documentation:
https://developer.arm.com/documentation/111078/latest

Change-Id: Id9b73799696a5ce04e656e07e4ddb548c5a7b042
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpus): workaround for C1-Premium erratum 3926381

C1-Premium erratum 3926381 is a Cat B erratum that applies
to revision r1p0 and is still open.

This errata can be avoided by converting WFx and

fix(cpus): workaround for C1-Premium erratum 3926381

C1-Premium erratum 3926381 is a Cat B erratum that applies
to revision r1p0 and is still open.

This errata can be avoided by converting WFx and WFxT
instructions to NOP when PSTATE.SM=1. After it is applied,
the code only converts WFx and WFxT instructions to NOP when
PSTATE.SM=1 or when PSTATE.ZA=1.

SDEN documentation:
https://developer.arm.com/documentation/111078/8-0/?lang=en

Change-Id: I24483fa88c6292f6dbe2950ebef88eebb5cc4e8d
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpus): workaround for C1-Premium erratum 3865171

C1-Premium erratum 3865171 is a Cat B erratum that applies
to revisions r0p0, r1p0 and is still open.

The erratum can be avoided by setting CPUA

fix(cpus): workaround for C1-Premium erratum 3865171

C1-Premium erratum 3865171 is a Cat B erratum that applies
to revisions r0p0, r1p0 and is still open.

The erratum can be avoided by setting CPUACTLR2_EL1[22] to 1,
which will disable linking multiple Non-Cacheable or Device
GRE loads to the same read request for the cache-line. This
might have a significant performance impact to Non-cacheable
and Device GRE read bandwidth for streaming scenarios.

SDEN documentation:
https://developer.arm.com/documentation/111078/latest

Change-Id: I0b97dfc1dd989e4d3e35716b0163b99c9719a0e6
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpus): workaround for C1-Premium erratum 3815514

C1-Premium erratum 3815514 is a Cat B erratum that applies
to revisions r0p0, r1p0 and is still open.

The erratum can be avoided by setting CPUA

fix(cpus): workaround for C1-Premium erratum 3815514

C1-Premium erratum 3815514 is a Cat B erratum that applies
to revisions r0p0, r1p0 and is still open.

The erratum can be avoided by setting CPUACTLR5[13] to 1.
This is expected to result in a small performance degradation
for workloads that use MTE. The degradation might be
approximately 1.6% when using MTE imprecise mode or 0.9% for
MTE precise mode.

SDEN documentation:
https://developer.arm.com/documentation/111078/latest

Change-Id: Id52a1a077459bd16de16b1ae00fc783250d197ed
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpus): workaround for C1-Premium erratum 3705939

C1-Premium erratum 3705939 is a Cat B erratum that applies
to revisions r0p0, r1p0 and is still open.

The erratum can be avoided by setting CPUA

fix(cpus): workaround for C1-Premium erratum 3705939

C1-Premium erratum 3705939 is a Cat B erratum that applies
to revisions r0p0, r1p0 and is still open.

The erratum can be avoided by setting CPUACTLR_EL1[48] to 1,
which disables a RDFFR optimization. Setting this bit has
negligible impact on GB6/SPECint performance, but will have an impact
on SVE RDFFR performance. Please contact Arm for more details.

SDEN documentation:
https://developer.arm.com/documentation/111078/latest

Change-Id: I4dc68f8fcb6275eab158c7fa6491536c62060ac0
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpus): workaround for C1-Premium erratum 3684152

C1-Premium erratum 3684152 is a Cat B erratum that applies
to revision r0p0, and it is fixed in r1p0.

The erratum can be avoided by setting CPUA

fix(cpus): workaround for C1-Premium erratum 3684152

C1-Premium erratum 3684152 is a Cat B erratum that applies
to revision r0p0, and it is fixed in r1p0.

The erratum can be avoided by setting CPUACTLR_EL1[60:58] to
3'b001, which has a small performance impact.

SDEN documentation:
https://developer.arm.com/documentation/111078/latest

Change-Id: I2e677b0e6cf3ce453eae54300c5c0072d734a341
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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