Searched hist:"68 ac5ed0493b24e6a0a178171a47db75a31cc423" (Results 1 – 5 of 5) sorted by relevance
| /rk3399_ARM-atf/lib/extensions/sve/ |
| H A D | sve.c | 68ac5ed0493b24e6a0a178171a47db75a31cc423 Thu Jul 08 08:35:57 UTC 2021 Arunachalam Ganapathy <arunachalam.ganapathy@arm.com> fix(el3_runtime): fix SVE and AMU extension enablement flags
If SVE are enabled for both Non-secure and Secure world along with AMU
extension, then it causes the TAM_BIT in CPTR_EL3 to be set upon exit
from bl31. This restricts access to the AMU register set in normal
world. This fix maintains consistency in both TAM_BIT and CPTR_EZ_BIT
by saving and restoring CPTR_EL3 register from EL3 context.
Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
Change-Id: Id76ce1d27ee48bed65eb32392036377716aff087
|
| /rk3399_ARM-atf/include/lib/extensions/ |
| H A D | amu.h | 68ac5ed0493b24e6a0a178171a47db75a31cc423 Thu Jul 08 08:35:57 UTC 2021 Arunachalam Ganapathy <arunachalam.ganapathy@arm.com> fix(el3_runtime): fix SVE and AMU extension enablement flags
If SVE are enabled for both Non-secure and Secure world along with AMU
extension, then it causes the TAM_BIT in CPTR_EL3 to be set upon exit
from bl31. This restricts access to the AMU register set in normal
world. This fix maintains consistency in both TAM_BIT and CPTR_EZ_BIT
by saving and restoring CPTR_EL3 register from EL3 context.
Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
Change-Id: Id76ce1d27ee48bed65eb32392036377716aff087
|
| /rk3399_ARM-atf/lib/extensions/amu/aarch64/ |
| H A D | amu.c | 68ac5ed0493b24e6a0a178171a47db75a31cc423 Thu Jul 08 08:35:57 UTC 2021 Arunachalam Ganapathy <arunachalam.ganapathy@arm.com> fix(el3_runtime): fix SVE and AMU extension enablement flags
If SVE are enabled for both Non-secure and Secure world along with AMU
extension, then it causes the TAM_BIT in CPTR_EL3 to be set upon exit
from bl31. This restricts access to the AMU register set in normal
world. This fix maintains consistency in both TAM_BIT and CPTR_EZ_BIT
by saving and restoring CPTR_EL3 register from EL3 context.
Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
Change-Id: Id76ce1d27ee48bed65eb32392036377716aff087
|
| /rk3399_ARM-atf/lib/el3_runtime/aarch64/ |
| H A D | context.S | 68ac5ed0493b24e6a0a178171a47db75a31cc423 Thu Jul 08 08:35:57 UTC 2021 Arunachalam Ganapathy <arunachalam.ganapathy@arm.com> fix(el3_runtime): fix SVE and AMU extension enablement flags
If SVE are enabled for both Non-secure and Secure world along with AMU
extension, then it causes the TAM_BIT in CPTR_EL3 to be set upon exit
from bl31. This restricts access to the AMU register set in normal
world. This fix maintains consistency in both TAM_BIT and CPTR_EZ_BIT
by saving and restoring CPTR_EL3 register from EL3 context.
Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
Change-Id: Id76ce1d27ee48bed65eb32392036377716aff087
|
| H A D | context_mgmt.c | 68ac5ed0493b24e6a0a178171a47db75a31cc423 Thu Jul 08 08:35:57 UTC 2021 Arunachalam Ganapathy <arunachalam.ganapathy@arm.com> fix(el3_runtime): fix SVE and AMU extension enablement flags
If SVE are enabled for both Non-secure and Secure world along with AMU
extension, then it causes the TAM_BIT in CPTR_EL3 to be set upon exit
from bl31. This restricts access to the AMU register set in normal
world. This fix maintains consistency in both TAM_BIT and CPTR_EZ_BIT
by saving and restoring CPTR_EL3 register from EL3 context.
Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
Change-Id: Id76ce1d27ee48bed65eb32392036377716aff087
|