1 /*
2 * Copyright (c) 2017-2025, Arm Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #ifndef AMU_H
8 #define AMU_H
9
10 #include <stdbool.h>
11 #include <stdint.h>
12
13 #include <context.h>
14
15 #include <platform_def.h>
16
17 #if ENABLE_FEAT_AMU
18 #if __aarch64__
19 void amu_enable(cpu_context_t *ctx);
20 void amu_init_el3(unsigned int core_pos);
21 void amu_init_el2_unused(void);
22 void amu_enable_per_world(per_world_context_t *per_world_ctx);
23 #else
24 void amu_enable(bool el2_unused);
25 #endif /* __aarch64__ */
26
27 #else
28 #if __aarch64__
amu_enable(cpu_context_t * ctx)29 void amu_enable(cpu_context_t *ctx)
30 {
31 }
amu_init_el3(unsigned int core_pos)32 void amu_init_el3(unsigned int core_pos)
33 {
34 }
amu_init_el2_unused(void)35 void amu_init_el2_unused(void)
36 {
37 }
amu_enable_per_world(per_world_context_t * per_world_ctx)38 void amu_enable_per_world(per_world_context_t *per_world_ctx)
39 {
40 }
41 #else
amu_enable(bool el2_unused)42 static inline void amu_enable(bool el2_unused)
43 {
44 }
45 #endif /*__aarch64__ */
46 #endif /* ENABLE_FEAT_AMU */
47
48 /*
49 * Per-core list of the counters to be enabled. Value will be written into
50 * AMCNTENSET1_EL0 verbatim.
51 */
52 #if ENABLE_AMU_AUXILIARY_COUNTERS
53 extern uint16_t plat_amu_aux_enables[PLATFORM_CORE_COUNT];
54 #endif
55
56 #define CTX_AMU_GRP0_ALL U(4)
57 #define CTX_AMU_GRP1_ALL U(16)
58
59 typedef struct amu_regs {
60 u_register_t grp0[CTX_AMU_GRP0_ALL];
61 #if ENABLE_AMU_AUXILIARY_COUNTERS
62 u_register_t grp1[CTX_AMU_GRP1_ALL];
63 #endif
64 } amu_regs_t;
65
read_amu_grp0_ctx_reg(amu_regs_t * ctx,size_t index)66 static inline u_register_t read_amu_grp0_ctx_reg(amu_regs_t *ctx, size_t index)
67 {
68 return ctx->grp0[index];
69 }
70
write_amu_grp0_ctx_reg(amu_regs_t * ctx,size_t index,u_register_t val)71 static inline void write_amu_grp0_ctx_reg(amu_regs_t *ctx, size_t index, u_register_t val)
72 {
73 ctx->grp0[index] = val;
74 }
75
get_amu_aux_enables(size_t index)76 static inline uint16_t get_amu_aux_enables(size_t index)
77 {
78 #if ENABLE_AMU_AUXILIARY_COUNTERS
79 return plat_amu_aux_enables[index];
80 #else
81 return 0;
82 #endif
83 }
84
read_amu_grp1_ctx_reg(amu_regs_t * ctx,size_t index)85 static inline u_register_t read_amu_grp1_ctx_reg(amu_regs_t *ctx, size_t index)
86 {
87 #if ENABLE_AMU_AUXILIARY_COUNTERS
88 return ctx->grp1[index];
89 #else
90 return 0;
91 #endif
92 }
93
write_amu_grp1_ctx_reg(amu_regs_t * ctx,size_t index,u_register_t val)94 static inline void write_amu_grp1_ctx_reg(amu_regs_t *ctx, size_t index, u_register_t val)
95 {
96 #if ENABLE_AMU_AUXILIARY_COUNTERS
97 ctx->grp1[index] = val;
98 #endif
99 }
100
101 #endif /* AMU_H */
102