| /rk3399_ARM-atf/plat/intel/soc/common/aarch64/ |
| H A D | plat_helpers.S | 646a9a16150066eaa3146d4e2819d589333b6454 Tue Dec 24 02:46:44 UTC 2024 Jit Loon Lim <jit.loon.lim@altera.com> fix(intel): update warm reset routine and bootscratch register usage
Agilex5 platform:
Boot scratch COLD6 register is meant for Customer use only.
So, use Intel specific COLD3 register with [5:2]bits to
determine the warm reset and SMP boot requests.
Also handle the unaligned DEVICE/IO memory store and load
in the assembly entrypoint startup code.
Agilex, Stratix10, N5X platforms:
Use only the LSB 4bits [3:0] of the boot scratch COLD6 register
to detect the warm reset request.
Change-Id: I4fd6e63fe0bd42ddcb4a3f81c7a7295bdc8ca65f
Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>
|
| /rk3399_ARM-atf/plat/intel/soc/agilex5/ |
| H A D | bl31_plat_setup.c | 646a9a16150066eaa3146d4e2819d589333b6454 Tue Dec 24 02:46:44 UTC 2024 Jit Loon Lim <jit.loon.lim@altera.com> fix(intel): update warm reset routine and bootscratch register usage
Agilex5 platform:
Boot scratch COLD6 register is meant for Customer use only.
So, use Intel specific COLD3 register with [5:2]bits to
determine the warm reset and SMP boot requests.
Also handle the unaligned DEVICE/IO memory store and load
in the assembly entrypoint startup code.
Agilex, Stratix10, N5X platforms:
Use only the LSB 4bits [3:0] of the boot scratch COLD6 register
to detect the warm reset request.
Change-Id: I4fd6e63fe0bd42ddcb4a3f81c7a7295bdc8ca65f
Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>
|
| /rk3399_ARM-atf/plat/intel/soc/n5x/include/ |
| H A D | socfpga_plat_def.h | 646a9a16150066eaa3146d4e2819d589333b6454 Tue Dec 24 02:46:44 UTC 2024 Jit Loon Lim <jit.loon.lim@altera.com> fix(intel): update warm reset routine and bootscratch register usage
Agilex5 platform:
Boot scratch COLD6 register is meant for Customer use only.
So, use Intel specific COLD3 register with [5:2]bits to
determine the warm reset and SMP boot requests.
Also handle the unaligned DEVICE/IO memory store and load
in the assembly entrypoint startup code.
Agilex, Stratix10, N5X platforms:
Use only the LSB 4bits [3:0] of the boot scratch COLD6 register
to detect the warm reset request.
Change-Id: I4fd6e63fe0bd42ddcb4a3f81c7a7295bdc8ca65f
Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>
|
| /rk3399_ARM-atf/plat/intel/soc/common/ |
| H A D | socfpga_psci.c | 646a9a16150066eaa3146d4e2819d589333b6454 Tue Dec 24 02:46:44 UTC 2024 Jit Loon Lim <jit.loon.lim@altera.com> fix(intel): update warm reset routine and bootscratch register usage
Agilex5 platform:
Boot scratch COLD6 register is meant for Customer use only.
So, use Intel specific COLD3 register with [5:2]bits to
determine the warm reset and SMP boot requests.
Also handle the unaligned DEVICE/IO memory store and load
in the assembly entrypoint startup code.
Agilex, Stratix10, N5X platforms:
Use only the LSB 4bits [3:0] of the boot scratch COLD6 register
to detect the warm reset request.
Change-Id: I4fd6e63fe0bd42ddcb4a3f81c7a7295bdc8ca65f
Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>
|
| /rk3399_ARM-atf/plat/intel/soc/agilex5/include/ |
| H A D | socfpga_plat_def.h | 646a9a16150066eaa3146d4e2819d589333b6454 Tue Dec 24 02:46:44 UTC 2024 Jit Loon Lim <jit.loon.lim@altera.com> fix(intel): update warm reset routine and bootscratch register usage
Agilex5 platform:
Boot scratch COLD6 register is meant for Customer use only.
So, use Intel specific COLD3 register with [5:2]bits to
determine the warm reset and SMP boot requests.
Also handle the unaligned DEVICE/IO memory store and load
in the assembly entrypoint startup code.
Agilex, Stratix10, N5X platforms:
Use only the LSB 4bits [3:0] of the boot scratch COLD6 register
to detect the warm reset request.
Change-Id: I4fd6e63fe0bd42ddcb4a3f81c7a7295bdc8ca65f
Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>
|
| /rk3399_ARM-atf/plat/intel/soc/common/include/ |
| H A D | platform_def.h | 646a9a16150066eaa3146d4e2819d589333b6454 Tue Dec 24 02:46:44 UTC 2024 Jit Loon Lim <jit.loon.lim@altera.com> fix(intel): update warm reset routine and bootscratch register usage
Agilex5 platform:
Boot scratch COLD6 register is meant for Customer use only.
So, use Intel specific COLD3 register with [5:2]bits to
determine the warm reset and SMP boot requests.
Also handle the unaligned DEVICE/IO memory store and load
in the assembly entrypoint startup code.
Agilex, Stratix10, N5X platforms:
Use only the LSB 4bits [3:0] of the boot scratch COLD6 register
to detect the warm reset request.
Change-Id: I4fd6e63fe0bd42ddcb4a3f81c7a7295bdc8ca65f
Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>
|
| /rk3399_ARM-atf/plat/intel/soc/stratix10/include/ |
| H A D | socfpga_plat_def.h | 646a9a16150066eaa3146d4e2819d589333b6454 Tue Dec 24 02:46:44 UTC 2024 Jit Loon Lim <jit.loon.lim@altera.com> fix(intel): update warm reset routine and bootscratch register usage
Agilex5 platform:
Boot scratch COLD6 register is meant for Customer use only.
So, use Intel specific COLD3 register with [5:2]bits to
determine the warm reset and SMP boot requests.
Also handle the unaligned DEVICE/IO memory store and load
in the assembly entrypoint startup code.
Agilex, Stratix10, N5X platforms:
Use only the LSB 4bits [3:0] of the boot scratch COLD6 register
to detect the warm reset request.
Change-Id: I4fd6e63fe0bd42ddcb4a3f81c7a7295bdc8ca65f
Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>
|
| /rk3399_ARM-atf/plat/intel/soc/agilex/include/ |
| H A D | socfpga_plat_def.h | 646a9a16150066eaa3146d4e2819d589333b6454 Tue Dec 24 02:46:44 UTC 2024 Jit Loon Lim <jit.loon.lim@altera.com> fix(intel): update warm reset routine and bootscratch register usage
Agilex5 platform:
Boot scratch COLD6 register is meant for Customer use only.
So, use Intel specific COLD3 register with [5:2]bits to
determine the warm reset and SMP boot requests.
Also handle the unaligned DEVICE/IO memory store and load
in the assembly entrypoint startup code.
Agilex, Stratix10, N5X platforms:
Use only the LSB 4bits [3:0] of the boot scratch COLD6 register
to detect the warm reset request.
Change-Id: I4fd6e63fe0bd42ddcb4a3f81c7a7295bdc8ca65f
Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>
|